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authorNicolas Pitre <nico@fluxnic.net>2011-05-03 15:30:34 -0400
committerNicolas Pitre <nico@fluxnic.net>2011-05-03 15:39:05 -0400
commitf5178ddd2f09de8b1cfc5e19043892e8b24666cb (patch)
tree1df301d8bf3b57a2c95a7b77270188909cce3a36 /arch/arm/boot/compressed
parent0ffd3c4805446dc00a042140443fd7342a35d0b4 (diff)
downloadop-kernel-dev-f5178ddd2f09de8b1cfc5e19043892e8b24666cb.zip
op-kernel-dev-f5178ddd2f09de8b1cfc5e19043892e8b24666cb.tar.gz
ARM: PJ4: remove the ARMv6 compatible cache method entries
The Marvell PJ4 is ARMv7 capable, so we don't support it in ARMv6 mode anymore. Signed-off-by: Nicolas Pitre <nico@fluxnic.net> Acked-by: Saeed Bishara <saeed.bishara@gmail.com> Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Diffstat (limited to 'arch/arm/boot/compressed')
-rw-r--r--arch/arm/boot/compressed/head.S6
1 files changed, 0 insertions, 6 deletions
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index adf583c..a36f452 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -735,12 +735,6 @@ proc_types:
W(b) __armv4_mmu_cache_off
W(b) __armv6_mmu_cache_flush
- .word 0x560f5810 @ Marvell PJ4 ARMv6
- .word 0xff0ffff0
- W(b) __armv4_mmu_cache_on
- W(b) __armv4_mmu_cache_off
- W(b) __armv6_mmu_cache_flush
-
.word 0x000f0000 @ new CPU Id
.word 0x000f0000
W(b) __armv7_mmu_cache_on
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