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| author | Doug Anderson <armlinux@m.disordat.com> | 2016-04-07 00:27:26 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@armlinux.org.uk> | 2016-07-14 15:32:31 +0100 |
| commit | 9f6f93543d473d656bdc5c94f567c7684e956e52 (patch) | |
| tree | 77e162b07a7e405724b0ddd00201005687ce64f8 /arch/arm/Kconfig | |
| parent | 416bcf21591850cd12066b2f11655695118e6908 (diff) | |
| download | op-kernel-dev-9f6f93543d473d656bdc5c94f567c7684e956e52.zip op-kernel-dev-9f6f93543d473d656bdc5c94f567c7684e956e52.tar.gz | |
ARM: 8560/1: errata: Workaround errata A12 825619 / A17 852421
The workaround for both errata is to set bit 24 in the diagnostic
register. There are no known end-user bugs solved by fixing this
errata, but the fix is trivial and it seems sane to apply it.
The arguments for why this needs to be in the kernel are similar to the
arugments made in the patch "Workaround errata A12 818325/852422 A17
852423".
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/Kconfig')
| -rw-r--r-- | arch/arm/Kconfig | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index ed275aa2..1be1022 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1210,6 +1210,24 @@ config ARM_ERRATA_821420 one is in the shadow of a branch or abort, can lead to a deadlock when the VMOV instructions are issued out-of-order. +config ARM_ERRATA_825619 + bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" + depends on CPU_V7 + help + This option enables the workaround for the 825619 Cortex-A12 + (all revs) erratum. Within rare timing constraints, executing a + DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable + and Device/Strongly-Ordered loads and stores might cause deadlock + +config ARM_ERRATA_852421 + bool "ARM errata: A17: DMB ST might fail to create order between stores" + depends on CPU_V7 + help + This option enables the workaround for the 852421 Cortex-A17 + (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, + execution of a DMB ST instruction might fail to properly order + stores from GroupA and stores from GroupB. + config ARM_ERRATA_852423 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" depends on CPU_V7 |
