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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2013-01-09 08:58:57 -0800 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2013-01-09 08:58:57 -0800 |
| commit | 5c49985c21bba4d2f899e3a97121868a5c58a876 (patch) | |
| tree | f877cde6c0effa6c8cd6e1d0d7e116358eb41ee8 /arch/arm/Kconfig | |
| parent | 57a0c1e2d6cb70ad0f8549ae730fc58fd0553429 (diff) | |
| parent | 8a3a180d21793f2e4386b3cb61c48322564fc80a (diff) | |
| download | op-kernel-dev-5c49985c21bba4d2f899e3a97121868a5c58a876.zip op-kernel-dev-5c49985c21bba4d2f899e3a97121868a5c58a876.tar.gz | |
Merge branch 'fixes' of git://git.linaro.org/people/rmk/linux-arm
Pull ARM fixes from Russell King.
* 'fixes' of git://git.linaro.org/people/rmk/linux-arm:
ARM: 7616/1: cache-l2x0: aurora: Use writel_relaxed instead of writel
ARM: 7615/1: cache-l2x0: aurora: Invalidate during clean operation with WT enable
ARM: 7614/1: mm: fix wrong branch from Cortex-A9 to PJ4b
ARM: 7612/1: imx: Do not select some errata that depends on !ARCH_MULTIPLATFORM
ARM: 7611/1: VIC: fix bug in VIC irqdomain code
ARM: 7610/1: versatile: bump IRQ numbers
ARM: 7609/1: disable errata work-arounds which access secure registers
ARM: 7608/1: l2x0: Only set .set_debug on PL310 r3p0 and earlier
Diffstat (limited to 'arch/arm/Kconfig')
| -rw-r--r-- | arch/arm/Kconfig | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index ab864d9..67874b8 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1229,6 +1229,7 @@ config ARM_ERRATA_430973 config ARM_ERRATA_458693 bool "ARM errata: Processor deadlock when a false hazard is created" depends on CPU_V7 + depends on !ARCH_MULTIPLATFORM help This option enables the workaround for the 458693 Cortex-A8 (r2p0) erratum. For very specific sequences of memory operations, it is @@ -1242,6 +1243,7 @@ config ARM_ERRATA_458693 config ARM_ERRATA_460075 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" depends on CPU_V7 + depends on !ARCH_MULTIPLATFORM help This option enables the workaround for the 460075 Cortex-A8 (r2p0) erratum. Any asynchronous access to the L2 cache may encounter a @@ -1254,6 +1256,7 @@ config ARM_ERRATA_460075 config ARM_ERRATA_742230 bool "ARM errata: DMB operation may be faulty" depends on CPU_V7 && SMP + depends on !ARCH_MULTIPLATFORM help This option enables the workaround for the 742230 Cortex-A9 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction @@ -1266,6 +1269,7 @@ config ARM_ERRATA_742230 config ARM_ERRATA_742231 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" depends on CPU_V7 && SMP + depends on !ARCH_MULTIPLATFORM help This option enables the workaround for the 742231 Cortex-A9 (r2p0..r2p2) erratum. Under certain conditions, specific to the @@ -1316,6 +1320,7 @@ config PL310_ERRATA_727915 config ARM_ERRATA_743622 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" depends on CPU_V7 + depends on !ARCH_MULTIPLATFORM help This option enables the workaround for the 743622 Cortex-A9 (r2p*) erratum. Under very rare conditions, a faulty @@ -1329,6 +1334,7 @@ config ARM_ERRATA_743622 config ARM_ERRATA_751472 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" depends on CPU_V7 + depends on !ARCH_MULTIPLATFORM help This option enables the workaround for the 751472 Cortex-A9 (prior to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the |
