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| author | Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> | 2017-08-14 19:12:11 +0300 |
|---|---|---|
| committer | Vineet Gupta <vgupta@synopsys.com> | 2017-09-01 11:26:25 -0700 |
| commit | f6a09bace0bb9587985b48ed652f2b292f8de0de (patch) | |
| tree | 2d6a466f2c83b0ced16455c8291052103309d881 /arch/arc | |
| parent | 9926c29f746d178400543e2056cee4d437e697f3 (diff) | |
| download | op-kernel-dev-f6a09bace0bb9587985b48ed652f2b292f8de0de.zip op-kernel-dev-f6a09bace0bb9587985b48ed652f2b292f8de0de.tar.gz | |
ARC: [plat-axs103] use clk driver #2: Add core pll node to DT to manage cpu clk
Add core pll node (core_clk) to manage cpu frequency.
core_clk represents pll itself.
input_clk represents clock signal source (basically xtal) which
comes to pll input.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Diffstat (limited to 'arch/arc')
| -rw-r--r-- | arch/arc/boot/dts/axc003.dtsi | 11 | ||||
| -rw-r--r-- | arch/arc/boot/dts/axc003_idu.dtsi | 11 |
2 files changed, 18 insertions, 4 deletions
diff --git a/arch/arc/boot/dts/axc003.dtsi b/arch/arc/boot/dts/axc003.dtsi index cc9239e..dca7e39 100644 --- a/arch/arc/boot/dts/axc003.dtsi +++ b/arch/arc/boot/dts/axc003.dtsi @@ -24,10 +24,17 @@ ranges = <0x00000000 0x0 0xf0000000 0x10000000>; - core_clk: core_clk { + input_clk: input-clk { #clock-cells = <0>; compatible = "fixed-clock"; - clock-frequency = <90000000>; + clock-frequency = <33333333>; + }; + + core_clk: core-clk@80 { + compatible = "snps,axs10x-arc-pll-clock"; + reg = <0x80 0x10>, <0x100 0x10>; + #clock-cells = <0>; + clocks = <&input_clk>; }; core_intc: archs-intc@cpu { diff --git a/arch/arc/boot/dts/axc003_idu.dtsi b/arch/arc/boot/dts/axc003_idu.dtsi index 4ebb2170..5b56bef 100644 --- a/arch/arc/boot/dts/axc003_idu.dtsi +++ b/arch/arc/boot/dts/axc003_idu.dtsi @@ -24,10 +24,17 @@ ranges = <0x00000000 0x0 0xf0000000 0x10000000>; - core_clk: core_clk { + input_clk: input-clk { #clock-cells = <0>; compatible = "fixed-clock"; - clock-frequency = <100000000>; + clock-frequency = <33333333>; + }; + + core_clk: core-clk@80 { + compatible = "snps,axs10x-arc-pll-clock"; + reg = <0x80 0x10>, <0x100 0x10>; + #clock-cells = <0>; + clocks = <&input_clk>; }; core_intc: archs-intc@cpu { |
