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| author | Vineet Gupta <vgupta@synopsys.com> | 2013-06-17 19:44:06 +0530 |
|---|---|---|
| committer | Vineet Gupta <vgupta@synopsys.com> | 2013-08-30 10:19:12 +0530 |
| commit | d091fcb97ff48a5cb6de19ad0881fb2c8e76dbc0 (patch) | |
| tree | c54e1ce880e399ed6a72c054f6cf244bc3752071 /arch/arc/mm/tlbex.S | |
| parent | 64b703ef276964b160a5e88df0764f254460cafb (diff) | |
| download | op-kernel-dev-d091fcb97ff48a5cb6de19ad0881fb2c8e76dbc0.zip op-kernel-dev-d091fcb97ff48a5cb6de19ad0881fb2c8e76dbc0.tar.gz | |
ARC: MMUv4 preps/2 - Reshuffle PTE bits
With previous commit freeing up PTE bits, reassign them so as to:
- Match the bit to H/w counterpart where possible
(e.g. MMUv2 GLOBAL/PRESENT, this avoids a shift in create_tlb())
- Avoid holes in _PAGE_xxx definitions
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Diffstat (limited to 'arch/arc/mm/tlbex.S')
| -rw-r--r-- | arch/arc/mm/tlbex.S | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/arch/arc/mm/tlbex.S b/arch/arc/mm/tlbex.S index ec382e5..50e83ca 100644 --- a/arch/arc/mm/tlbex.S +++ b/arch/arc/mm/tlbex.S @@ -229,9 +229,6 @@ ex_saved_reg1: sr r3, [ARC_REG_TLBPD1] ; these go in PD1 and r2, r0, PTE_BITS_IN_PD0 ; Extract other PTE flags: (V)alid, (G)lb -#if (CONFIG_ARC_MMU_VER <= 2) /* Neednot be done with v3 onwards */ - lsr r2, r2 ; shift PTE flags to match layout in PD0 -#endif lr r3,[ARC_REG_TLBPD0] ; MMU prepares PD0 with vaddr and asid |
