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author | Vineet Gupta <vgupta@synopsys.com> | 2015-11-17 17:46:48 +0530 |
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committer | Vineet Gupta <vgupta@synopsys.com> | 2015-11-17 22:05:30 +0530 |
commit | e81b75f7b206d4c44afd20354a66825239490109 (patch) | |
tree | 1fefc2f6d91f5183a21b6d0708908b2516a0f6ec /arch/arc/kernel/ctx_sw_asm.S | |
parent | b8628f3fe41c999b003c541c078312fcead960d6 (diff) | |
download | op-kernel-dev-e81b75f7b206d4c44afd20354a66825239490109.zip op-kernel-dev-e81b75f7b206d4c44afd20354a66825239490109.tar.gz |
ARC: remove SYNC from __switch_to()
SYNC in __switch_to() is a historic relic and not needed at all.
- In UP context it is obviously useless, why would we want to stall
the core for all updates to stack memory of t0 to complete before
loading kernel mode callee registers from t1 stack's memory.
- In SMP, there could be potential race in which outgoing task could
be concurrently picked for running on a different core, thus writes
to stack here need to be visible before the reads from stack on
other core. Peter confirmed that generic schedular already has needed
barriers (by way of rq lock) so there is no need for additional arch
barrier.
This came up when Noam was trying to replace this SYNC with EZChip
specific hardware thread scheduling instruction for their platform
support.
Link: http://lkml.kernel.org/r/20151102092654.GM17308@twins.programming.kicks-ass.net
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: linux-kernel@vger.kernel.org
Cc: Noam Camus <noamc@ezchip.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Diffstat (limited to 'arch/arc/kernel/ctx_sw_asm.S')
-rw-r--r-- | arch/arc/kernel/ctx_sw_asm.S | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/arch/arc/kernel/ctx_sw_asm.S b/arch/arc/kernel/ctx_sw_asm.S index e248594..e6890b1 100644 --- a/arch/arc/kernel/ctx_sw_asm.S +++ b/arch/arc/kernel/ctx_sw_asm.S @@ -44,9 +44,6 @@ __switch_to: * don't need to do anything special to return it */ - /* hardware memory barrier */ - sync - /* * switch to new task, contained in r1 * Temp reg r3 is required to get the ptr to store val |