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| author | Ingo Molnar <mingo@kernel.org> | 2017-10-23 13:30:47 +0200 |
|---|---|---|
| committer | Ingo Molnar <mingo@kernel.org> | 2017-10-23 13:30:47 +0200 |
| commit | f95b23a112f1a31ea042483540cd907b58d23a5f (patch) | |
| tree | 3d41d2f8cf1d66ed593deb12f25a30d2905eb077 /arch/arc/include/asm/arcregs.h | |
| parent | da20ab35180780e4a6eadc804544f1fa967f3567 (diff) | |
| parent | 58c3862b521ead4f69a24ef009a679cb3c519620 (diff) | |
| download | op-kernel-dev-f95b23a112f1a31ea042483540cd907b58d23a5f.zip op-kernel-dev-f95b23a112f1a31ea042483540cd907b58d23a5f.tar.gz | |
Merge branch 'x86/urgent' into x86/asm, to pick up dependent fixes
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'arch/arc/include/asm/arcregs.h')
| -rw-r--r-- | arch/arc/include/asm/arcregs.h | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h index ba8e802..b1c56d3 100644 --- a/arch/arc/include/asm/arcregs.h +++ b/arch/arc/include/asm/arcregs.h @@ -98,6 +98,7 @@ /* Auxiliary registers */ #define AUX_IDENTITY 4 +#define AUX_EXEC_CTRL 8 #define AUX_INTR_VEC_BASE 0x25 #define AUX_VOL 0x5e @@ -135,12 +136,12 @@ struct bcr_identity { #endif }; -struct bcr_isa { +struct bcr_isa_arcv2 { #ifdef CONFIG_CPU_BIG_ENDIAN unsigned int div_rem:4, pad2:4, ldd:1, unalign:1, atomic:1, be:1, - pad1:11, atomic1:1, ver:8; + pad1:12, ver:8; #else - unsigned int ver:8, atomic1:1, pad1:11, be:1, atomic:1, unalign:1, + unsigned int ver:8, pad1:12, be:1, atomic:1, unalign:1, ldd:1, pad2:4, div_rem:4; #endif }; @@ -263,13 +264,13 @@ struct cpuinfo_arc { struct cpuinfo_arc_mmu mmu; struct cpuinfo_arc_bpu bpu; struct bcr_identity core; - struct bcr_isa isa; + struct bcr_isa_arcv2 isa; const char *details, *name; unsigned int vec_base; struct cpuinfo_arc_ccm iccm, dccm; struct { unsigned int swap:1, norm:1, minmax:1, barrel:1, crc:1, swape:1, pad1:2, - fpu_sp:1, fpu_dp:1, pad2:6, + fpu_sp:1, fpu_dp:1, dual_iss_enb:1, dual_iss_exist:1, pad2:4, debug:1, ap:1, smart:1, rtt:1, pad3:4, timer0:1, timer1:1, rtc:1, gfrc:1, pad4:4; } extn; |
