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authorVineet Gupta <vgupta@synopsys.com>2015-08-19 17:23:58 +0530
committerVineet Gupta <vgupta@synopsys.com>2015-08-20 19:05:49 +0530
commit090749502ff20d7d9ec244036fe636b6bf0433b6 (patch)
tree52ce66c6c0a525b4a9eff0ee5917c52f72479ead /arch/arc/boot
parent6de6066c0d24a66df465cf87a4041ef7ef35ba6f (diff)
downloadop-kernel-dev-090749502ff20d7d9ec244036fe636b6bf0433b6.zip
op-kernel-dev-090749502ff20d7d9ec244036fe636b6bf0433b6.tar.gz
ARC: add/fix some comments in code - no functional change
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Diffstat (limited to 'arch/arc/boot')
-rw-r--r--arch/arc/boot/dts/axc003.dtsi13
1 files changed, 7 insertions, 6 deletions
diff --git a/arch/arc/boot/dts/axc003.dtsi b/arch/arc/boot/dts/axc003.dtsi
index 1cd5e82..846481f 100644
--- a/arch/arc/boot/dts/axc003.dtsi
+++ b/arch/arc/boot/dts/axc003.dtsi
@@ -72,12 +72,13 @@
};
/*
- * This INTC is actually connected to DW APB GPIO
- * which acts as a wire between MB INTC and CPU INTC.
- * GPIO INTC is configured in platform init code
- * and here we mimic direct connection from MB INTC to
- * CPU INTC, thus we set "interrupts = <7>" instead of
- * "interrupts = <12>"
+ * The DW APB ICTL intc on MB is connected to CPU intc via a
+ * DT "invisible" DW APB GPIO block, configured to simply pass thru
+ * interrupts - setup accordinly in platform init (plat-axs10x/ax10x.c)
+ *
+ * So here we mimic a direct connection betwen them, ignoring the
+ * ABPG GPIO. Thus set "interrupts = <24>" (DW APB GPIO to core)
+ * instead of "interrupts = <12>" (DW APB ICTL to DW APB GPIO)
*
* This intc actually resides on MB, but we move it here to
* avoid duplicating the MB dtsi file given that IRQ from
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