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author | Kees Cook <kees.cook@canonical.com> | 2011-07-06 18:10:34 -0700 |
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committer | H. Peter Anvin <hpa@zytor.com> | 2011-07-06 20:09:34 -0700 |
commit | 7a3136666bc0f0419f7aaa7b1fabb4b0e0a7fb76 (patch) | |
tree | 9d9e9f1de8ab1306b8b9d26aadb4a7f401323e69 /arch/Kconfig | |
parent | b49c78d4827be8d7e67e5b94adac6b30a4a9ad14 (diff) | |
download | op-kernel-dev-7a3136666bc0f0419f7aaa7b1fabb4b0e0a7fb76.zip op-kernel-dev-7a3136666bc0f0419f7aaa7b1fabb4b0e0a7fb76.tar.gz |
x86, suspend: Restore MISC_ENABLE MSR in realmode wakeup
Some BIOSes will reset the Intel MISC_ENABLE MSR (specifically the
XD_DISABLE bit) when resuming from S3, which can interact poorly with
ebba638ae723d8a8fc2f7abce5ec18b688b791d7. In 32bit PAE mode, this can
lead to a fault when EFER is restored by the kernel wakeup routines,
due to it setting the NX bit for a CPU that (thanks to the BIOS reset)
now incorrectly thinks it lacks the NX feature. (64bit is not affected
because it uses a common CPU bring-up that specifically handles the
XD_DISABLE bit.)
The need for MISC_ENABLE being restored so early is specific to the S3
resume path. Normally, MISC_ENABLE is saved in save_processor_state(),
but this happens after the resume header is created, so just reproduce
the logic here. (acpi_suspend_lowlevel() creates the header, calls
do_suspend_lowlevel, which calls save_processor_state(), so the saved
processor context isn't available during resume header creation.)
[ hpa: Consider for stable if OK in mainline ]
Signed-off-by: Kees Cook <kees.cook@canonical.com>
Link: http://lkml.kernel.org/r/20110707011034.GA8523@outflux.net
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Cc: Rafael J. Wysocki <rjw@sisk.pl>
Cc: <stable@kernel.org> 2.6.38+
Diffstat (limited to 'arch/Kconfig')
0 files changed, 0 insertions, 0 deletions