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| author | Stafford Horne <shorne@gmail.com> | 2017-10-30 21:38:35 +0900 |
|---|---|---|
| committer | Stafford Horne <shorne@gmail.com> | 2017-11-03 14:01:13 +0900 |
| commit | 9b54470afd836278a7e6f0f08194e2e2dca4b6eb (patch) | |
| tree | 5471b19b526dd33b375f2ce7b129fce5f226a794 /MAINTAINERS | |
| parent | fab8be88ac0478b0157859f74fad5088c292356b (diff) | |
| download | op-kernel-dev-9b54470afd836278a7e6f0f08194e2e2dca4b6eb.zip op-kernel-dev-9b54470afd836278a7e6f0f08194e2e2dca4b6eb.tar.gz | |
irqchip: add initial support for ompic
IPI driver for the Open Multi-Processor Interrupt Controller (ompic) as
described in the Multi-core support section of the OpenRISC 1.2
architecture specification:
https://github.com/openrisc/doc/raw/master/openrisc-arch-1.2-rev0.pdf
Each OpenRISC core contains a full interrupt controller which is used in
the SMP architecture for interrupt balancing. This IPI device, the
ompic, is the only external device required for enabling SMP on
OpenRISC.
Pending ops are stored in a memory bit mask which can allow multiple
pending operations to be set and serviced at a time. This is mostly
borrowed from the alpha IPI implementation.
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
[shorne@gmail.com: converted ops to bitmask, wrote commit message]
Signed-off-by: Stafford Horne <shorne@gmail.com>
Diffstat (limited to 'MAINTAINERS')
| -rw-r--r-- | MAINTAINERS | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index bcb7e25..bb129d5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -10034,6 +10034,7 @@ S: Maintained F: Documentation/devicetree/bindings/openrisc/ F: Documentation/openrisc/ F: arch/openrisc/ +F: drivers/irqchip/irq-ompic.c F: drivers/irqchip/irq-or1k-* OPENVSWITCH |
