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authorChristoffer Dall <christoffer.dall@linaro.org>2013-10-25 21:22:31 +0100
committerChristoffer Dall <christoffer.dall@linaro.org>2013-12-21 10:02:04 -0800
commit90a5355ee7639e92c0492ec592cba5c31bd80687 (patch)
tree7e0c7b4cc2195e0b2aa15c97578fbeb5c67cbacb /Kbuild
parentcbd333a4bfd0d93bba36d46a0e4e7979228873a6 (diff)
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op-kernel-dev-90a5355ee7639e92c0492ec592cba5c31bd80687.tar.gz
KVM: arm-vgic: Add GICD_SPENDSGIR and GICD_CPENDSGIR handlers
Handle MMIO accesses to the two registers which should support both the case where the VMs want to read/write either of these registers and the case where user space reads/writes these registers to do save/restore of the VGIC state. Note that the added complexity compared to simple set/clear enable registers stems from the bookkeping of source cpu ids. It may be possible to change the underlying data structure to simplify the complexity, but since this is not in the critical path at all, this will do. Also note that reading this register from a live guest will not be accurate compared to on hardware, because some state may be living on the CPU LRs and the only way to give a consistent read would be to force stop all the VCPUs and request them to unqueu the LR state onto the distributor. Until we have an actual user of live reading this register, we can live with the difference. Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
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