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| author | Maxime Ripard <maxime.ripard@free-electrons.com> | 2014-04-17 11:06:45 +0200 |
|---|---|---|
| committer | Daniel Lezcano <daniel.lezcano@linaro.org> | 2014-04-22 13:56:50 +0200 |
| commit | e50a00be5c420b4f28836dec281cdde4bed832a2 (patch) | |
| tree | ced5d90749486cf68f9c7f8c5a35365d5c8125a1 /Documentation | |
| parent | a5e11117856147bd35e740b36939f3a8a958e1e6 (diff) | |
| download | op-kernel-dev-e50a00be5c420b4f28836dec281cdde4bed832a2.zip op-kernel-dev-e50a00be5c420b4f28836dec281cdde4bed832a2.tar.gz | |
clocksource: sun5i: Add support for reset controller
The Allwinner A31 that uses this timer has the timer IP asserted in reset.
Add an optional reset property to the DT, and deassert the timer from reset if
it's there.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt b/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt index 7c26154..27cfc7d 100644 --- a/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt +++ b/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt @@ -9,6 +9,9 @@ Required properties: one) - clocks: phandle to the source clock (usually the AHB clock) +Optionnal properties: +- resets: phandle to a reset controller asserting the timer + Example: timer@01c60000 { @@ -19,4 +22,5 @@ timer@01c60000 { <0 53 1>, <0 54 1>; clocks = <&ahb1_gates 19>; + resets = <&ahb1rst 19>; }; |
