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authorChen-Yu Tsai <wens@csie.org>2014-01-17 21:24:47 +0800
committerDavid S. Miller <davem@davemloft.net>2014-01-19 20:02:41 -0800
commitaf0bd4e9ba809391f275d0c094ac0bfbfbb3f430 (patch)
tree883ebd0c4ccd98de59579a8b665ff7e7bbcf58e7 /Documentation
parent022066f50f53000679d31eb407693085f37b3f14 (diff)
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net: stmmac: sunxi platform extensions for GMAC in Allwinner A20 SoC's
The Allwinner A20 has an ethernet controller that seems to be an early version of Synopsys DesignWare MAC 10/100/1000 Universal, which is supported by the stmmac driver. Allwinner's GMAC requires setting additional registers in the SoC's clock control unit. The exact version of the DWMAC IP that Allwinner uses is unknown, thus the exact feature set is unknown. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'Documentation')
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+* Allwinner GMAC ethernet controller
+
+This device is a platform glue layer for stmmac.
+Please see stmmac.txt for the other unchanged properties.
+
+Required properties:
+ - compatible: Should be "allwinner,sun7i-a20-gmac"
+ - clocks: Should contain the GMAC main clock, and tx clock
+ The tx clock type should be "allwinner,sun7i-a20-gmac-clk"
+ - clock-names: Should contain the clock names "stmmaceth",
+ and "allwinner_gmac_tx"
+
+Optional properties:
+- phy-supply: phandle to a regulator if the PHY needs one
+
+Examples:
+
+ gmac: ethernet@01c50000 {
+ compatible = "allwinner,sun7i-a20-gmac";
+ reg = <0x01c50000 0x10000>,
+ <0x01c20164 0x4>;
+ interrupts = <0 85 1>;
+ interrupt-names = "macirq";
+ clocks = <&ahb_gates 49>, <&gmac_tx>;
+ clock-names = "stmmaceth", "allwinner_gmac_tx";
+ phy-mode = "mii";
+ };
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