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| author | Michael Witten <mfwitten@gmail.com> | 2011-08-29 16:00:55 +0000 |
|---|---|---|
| committer | Michael Witten <mfwitten@gmail.com> | 2011-08-29 20:00:24 +0000 |
| commit | 2d43f5d667273ba4975cb79782a46aa374dd8607 (patch) | |
| tree | fed80399516beeb604ab9a99fc3074e25539a511 /Documentation | |
| parent | 0c2d91a80a156208d2f9f3dfb01871ebcf4a9338 (diff) | |
| download | op-kernel-dev-2d43f5d667273ba4975cb79782a46aa374dd8607.zip op-kernel-dev-2d43f5d667273ba4975cb79782a46aa374dd8607.tar.gz | |
DocBook/drm: Improve flow of GPU/CPU coherence sentence
Signed-off-by: Michael Witten <mfwitten@gmail.com>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/DocBook/drm.tmpl | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/Documentation/DocBook/drm.tmpl b/Documentation/DocBook/drm.tmpl index c358367..ba20f9f 100644 --- a/Documentation/DocBook/drm.tmpl +++ b/Documentation/DocBook/drm.tmpl @@ -720,8 +720,9 @@ void intel_crt_init(struct drm_device *dev) provides memory to back each object. When mapped into the GTT or used in a command buffer, the backing pages for an object are flushed to memory and marked write combined so as to be coherent - with the GPU. Likewise, when the GPU finishes rendering to an object, - if the CPU accesses it, it must be made coherent with the CPU's view + with the GPU. Likewise, if the CPU accesses an object after the GPU + has finished rendering to the object, then the object must be made + coherent with the CPU's view of memory, usually involving GPU cache flushing of various kinds. This core CPU<->GPU coherency management is provided by the GEM set domain function, which evaluates an object's current domain and |
