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| author | Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> | 2015-01-06 00:25:08 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2015-01-08 16:14:31 +0100 |
| commit | 90cf0e2b9660f16f944b892c2d2a08b4e0a551a8 (patch) | |
| tree | 3b1163eb2c032dd8799224108be2d810efc2ceb3 /Documentation | |
| parent | a2868160f402e0282611cfe72ea0d8b5e57f7aa0 (diff) | |
| download | op-kernel-dev-90cf0e2b9660f16f944b892c2d2a08b4e0a551a8.zip op-kernel-dev-90cf0e2b9660f16f944b892c2d2a08b4e0a551a8.tar.gz | |
clk: shmobile: Add R-Car Gen2 RCAN clock support
Add the RCAN clock support to the R-Car generation 2 CPG driver. This clock
gets derived from the USB_EXTAL clock, dividing it by 6. The layout of the
RCANCKCR register is similar to those of the clocks supported by the 'clk-div6'
driver but has no divider field, and so can't be supported by that driver...
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt index fc7ef99..5b704b5 100644 --- a/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt +++ b/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt @@ -14,10 +14,11 @@ Required Properties: - reg: Base address and length of the memory resource used by the CPG - - clocks: Reference to the parent clock + - clocks: References to the parent clocks: first to the EXTAL clock, second + to the USB_EXTAL clock - #clock-cells: Must be 1 - clock-output-names: The names of the clocks. Supported clocks are "main", - "pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "sd1" and "z" + "pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "sd1", "z", and "rcan" Example @@ -27,8 +28,9 @@ Example compatible = "renesas,r8a7790-cpg-clocks", "renesas,rcar-gen2-cpg-clocks"; reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>; + clocks = <&extal_clk &usb_extal_clk>; #clock-cells = <1>; clock-output-names = "main", "pll0, "pll1", "pll3", - "lb", "qspi", "sdh", "sd0", "sd1", "z"; + "lb", "qspi", "sdh", "sd0", "sd1", "z", + "rcan"; }; |
