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author | Hans de Goede <hdegoede@redhat.com> | 2014-11-16 13:56:57 +0100 |
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committer | Maxime Ripard <maxime.ripard@free-electrons.com> | 2014-11-23 17:02:57 +0100 |
commit | c1ec51603053260b138fc98e2ed18a5a9bea4515 (patch) | |
tree | bc00330e624ba3df280e677d4a28cf2394c2f382 /Documentation | |
parent | 95e94c1fadcd1959857db45c2e11810a893badd0 (diff) | |
download | op-kernel-dev-c1ec51603053260b138fc98e2ed18a5a9bea4515.zip op-kernel-dev-c1ec51603053260b138fc98e2ed18a5a9bea4515.tar.gz |
clk: sunxi: gmac-tx-clk mux is not a CLK_MUX_INDEX_BIT mux
A CLK_MUX_INDEX_BIT mux has one bit per parent, but the sun7i-a20-gmac-clk
has 2 bits selecting between 3 possible parents using values of 0, 1, 2,
which makes it a regular mux which should not have CLK_MUX_INDEX_BIT set in
its flag.
However we do not support parent 1 (an external clock), so use a table to
select parent 0 or 2, which are the 2 parents we support.
Note this has not been causing any issues sofar, because we start with a
parent setting of parent 0, and only ever re-parent to parent 2 (for which
we use an index of 1 as we skip parent 1) and with CLK_MUX_INDEX_BIT set
we write a value of 2 for index 1.
Tested on both a cubietruck (which uses rgmii mode) as well as a cs908
(an a31s board which uses mii mode).
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'Documentation')
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