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authorEmilio López <emilio@elopez.com.ar>2013-12-23 00:32:39 -0300
committerEmilio López <emilio@elopez.com.ar>2013-12-28 17:08:22 -0300
commit7551769a225f3e600d6455e63ae00d51df37ff59 (patch)
treee2682fcc3bd43d228022be9be528f5ac58ab5046 /Documentation
parentd584c1331d6421e2387eab10b11fa6f08b4a4b5f (diff)
downloadop-kernel-dev-7551769a225f3e600d6455e63ae00d51df37ff59.zip
op-kernel-dev-7551769a225f3e600d6455e63ae00d51df37ff59.tar.gz
clk: sunxi: mod0 support
This commit implements support for the "module 0" type of clocks, as used by MMC, IR, NAND, SATA and other components. Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/clock/sunxi.txt5
1 files changed, 4 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
index 80b2a39..46d8433 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -35,10 +35,13 @@ Required properties:
"allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20
"allwinner,sun6i-a31-apb2-div-clk" - for the APB2 gates on A31
"allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
+ "allwinner,sun4i-mod0-clk" - for the module 0 family of clocks
Required properties for all clocks:
- reg : shall be the control register address for the clock.
-- clocks : shall be the input parent clock(s) phandle for the clock
+- clocks : shall be the input parent clock(s) phandle for the clock. For
+ multiplexed clocks, the list order must match the hardware
+ programming order.
- #clock-cells : from common clock binding; shall be set to 0 except for
"allwinner,*-gates-clk" where it shall be set to 1
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