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authorNaveen Krishna Ch <naveenkrishna.ch@gmail.com>2014-10-21 11:13:52 +0530
committerSylwester Nawrocki <s.nawrocki@samsung.com>2014-10-31 10:45:51 +0100
commit6d0c8c723f0b886f58263c089831fd2bee0b3b57 (patch)
treeab824227dc59d57fa769b2fe07fca91ac391f097 /Documentation
parent57a2b485fa512be47b479077b5f89e1bfe536709 (diff)
downloadop-kernel-dev-6d0c8c723f0b886f58263c089831fd2bee0b3b57.zip
op-kernel-dev-6d0c8c723f0b886f58263c089831fd2bee0b3b57.tar.gz
clk: samsung: exynos7: add clocks for MMC block
Exynos7 supports 3 MMC channels, add the MMC gate clocks to support them. Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/clock/exynos7-clock.txt21
1 files changed, 21 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/exynos7-clock.txt b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
index 789f761..b29cb50 100644
--- a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
@@ -27,9 +27,12 @@ Required Properties for Clock Controller:
- "samsung,exynos7-clock-topc"
- "samsung,exynos7-clock-top0"
+ - "samsung,exynos7-clock-top1"
- "samsung,exynos7-clock-peric0"
- "samsung,exynos7-clock-peric1"
- "samsung,exynos7-clock-peris"
+ - "samsung,exynos7-clock-fsys0"
+ - "samsung,exynos7-clock-fsys1"
- reg: physical base address of the controller and the length of
memory mapped region.
@@ -50,6 +53,13 @@ Input clocks for top0 clock controller:
- dout_sclk_cc_pll
- dout_sclk_mfc_pll
+Input clocks for top1 clock controller:
+ - fin_pll
+ - dout_sclk_bus0_pll
+ - dout_sclk_bus1_pll
+ - dout_sclk_cc_pll
+ - dout_sclk_mfc_pll
+
Input clocks for peric0 clock controller:
- fin_pll
- dout_aclk_peric0_66
@@ -65,3 +75,14 @@ Input clocks for peric1 clock controller:
Input clocks for peris clock controller:
- fin_pll
- dout_aclk_peris_66
+
+Input clocks for fsys0 clock controller:
+ - fin_pll
+ - dout_aclk_fsys0_200
+ - dout_sclk_mmc2
+
+Input clocks for fsys1 clock controller:
+ - fin_pll
+ - dout_aclk_fsys1_200
+ - dout_sclk_mmc0
+ - dout_sclk_mmc1
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