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authorPaul E. McKenney <paulmck@linux.vnet.ibm.com>2014-05-13 10:14:51 -0700
committerPaul E. McKenney <paulmck@linux.vnet.ibm.com>2014-07-08 08:13:03 -0700
commit5726ce06ad6bcd8dd75a204d1465c99a2f897d3a (patch)
treec3240a49d769fc49f0fee614f63c897ddce87f3b /Documentation
parent4a81e8328d3791a4f99bf5b436d050f6dc5ffea3 (diff)
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documentation: Clarify wake-up/memory-barrier relationship
This commit adds an example demonstrating that if a wake_up() doesn't actually wake something up, no memory ordering is provided. Reported-by: Peter Zijlstra <peterz@infradead.org> Signed-off-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com> Reviewed-by: Josh Triplett <josh@joshtriplett.org> Reviewed-by: Lai Jiangshan <laijs@cn.fujitsu.com> Acked-by: Peter Zijlstra <peterz@infradead.org>
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/memory-barriers.txt15
1 files changed, 15 insertions, 0 deletions
diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt
index f1dc4a2..a6ca533 100644
--- a/Documentation/memory-barriers.txt
+++ b/Documentation/memory-barriers.txt
@@ -1893,6 +1893,21 @@ between the STORE to indicate the event and the STORE to set TASK_RUNNING:
<general barrier> STORE current->state
LOAD event_indicated
+To repeat, this write memory barrier is present if and only if something
+is actually awakened. To see this, consider the following sequence of
+events, where X and Y are both initially zero:
+
+ CPU 1 CPU 2
+ =============================== ===============================
+ X = 1; STORE event_indicated
+ smp_mb(); wake_up();
+ Y = 1; wait_event(wq, Y == 1);
+ wake_up(); load from Y sees 1, no memory barrier
+ load from X might see 0
+
+In contrast, if a wakeup does occur, CPU 2's load from X would be guaranteed
+to see 1.
+
The available waker functions include:
complete();
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