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| author | Florian Fainelli <f.fainelli@gmail.com> | 2016-02-03 18:14:51 -0800 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2016-05-09 12:00:01 +0200 |
| commit | a5b143ec51bbfda3dc385e51f8c404fb415be691 (patch) | |
| tree | 6abf1d48b81d7d4d50a53fc159e2c863c43b94df /Documentation/parport.txt | |
| parent | f241265fdcc37a171ba246780462e19960a49e7f (diff) | |
| download | op-kernel-dev-a5b143ec51bbfda3dc385e51f8c404fb415be691.zip op-kernel-dev-a5b143ec51bbfda3dc385e51f8c404fb415be691.tar.gz | |
MIPS: BMIPS: Add missing 7038 L1 register cells to BCM7435
7435 has 4 7038 L1 base register address for each of its Core + TP (for a total
of 4 threads of execution), add the two missing cells for Core 1. We are
providing HW interrupts 2/3 even for Core 1/TP0/TP1 because that's what they
are, and we can later decide to remap these in software to provide proper
interrupt affinity/parenting.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Cc: john@phrozen.org
Cc: cernekee@gmail.com
Cc: jon.fraser@broadcom.com
Cc: jaedon.shin@gmail.com
Cc: dragan.stancevic@gmail.com
Cc: jogo@openwrt.org
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/12378/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'Documentation/parport.txt')
0 files changed, 0 insertions, 0 deletions
