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author | Santosh Shilimkar <santosh.shilimkar@ti.com> | 2013-09-27 21:56:31 +0100 |
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committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2013-10-03 10:39:44 +0100 |
commit | bc41b8724f24b9a27d1dcc6c974b8f686b38d554 (patch) | |
tree | 3572fd34c6dd22e6b72c0a855ac8943921d419ad /Documentation/padata.txt | |
parent | 856337283a215b9f92189f22862e4415f4d6bd85 (diff) | |
download | op-kernel-dev-bc41b8724f24b9a27d1dcc6c974b8f686b38d554.zip op-kernel-dev-bc41b8724f24b9a27d1dcc6c974b8f686b38d554.tar.gz |
ARM: 7846/1: Update SMP_ON_UP code to detect A9MPCore with 1 CPU devices
The generic code is well equipped to differentiate between
SMP and UP configurations.However, there are some devices which
use Cortex-A9 MP core IP with 1 CPU as configuration. To let
these SOCs to co-exist in a CONFIG_SMP=y build by leveraging
the SMP_ON_UP support, we need to additionally check the
number the cores in Cortex-A9 MPCore configuration. Without
such a check in place, the startup code tries to execute
ALT_SMP() set of instructions which lead to CPU faults.
The issue was spotted on TI's Aegis device and this patch
makes now the device work with omap2plus_defconfig which
enables SMP by default. The change is kept limited to only
Cortex-A9 MPCore detection code.
Note that if any future SoC *does* use 0x0 as the PERIPH_BASE, then
the SCU address check code needs to be #ifdef'd for for the Aegis
platform.
Acked-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'Documentation/padata.txt')
0 files changed, 0 insertions, 0 deletions