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authorRobert Richter <robert.richter@amd.com>2011-02-02 17:36:12 +0100
committerIngo Molnar <mingo@elte.hu>2011-02-16 13:30:53 +0100
commit4979d2729af22f6ce8faa325fc60a85a2c2daa02 (patch)
tree5c08ce1b206375eb457f1d467f5eeac6981c8954 /Documentation/hw_random.txt
parent73d6e52206a20354738418625cedc244cbfd5023 (diff)
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perf, x86: Add support for AMD family 15h core counters
This patch adds support for AMD family 15h core counters. There are major changes compared to family 10h. First, there is a new perfctr msr range for up to 6 counters. Northbridge counters are separate now. This patch only adds support for core counters. Second, certain events may only be scheduled on certain counters. For this we need to extend the event scheduling and constraints. We use cpu feature flags to calculate family 15h msr address offsets. This way we later can implement a faster ALTERNATIVE() version for this. Signed-off-by: Robert Richter <robert.richter@amd.com> Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> LKML-Reference: <20110215135210.GB5874@erda.amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
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