summaryrefslogtreecommitdiffstats
path: root/Documentation/devicetree
diff options
context:
space:
mode:
authorOlof Johansson <olof@lixom.net>2015-01-23 14:53:54 -0800
committerOlof Johansson <olof@lixom.net>2015-01-23 14:53:54 -0800
commit82483ad67e965f6edd61c6c2cdb4ba295cf0af96 (patch)
tree22708288cab53cfd07b63a2bd5b11ee8771a8b0e /Documentation/devicetree
parent085dd64e537b06c7b741dac5f0ff3734d27f9a13 (diff)
parent3568df3d31d62b4368830cc6aac868cecdefd187 (diff)
downloadop-kernel-dev-82483ad67e965f6edd61c6c2cdb4ba295cf0af96.zip
op-kernel-dev-82483ad67e965f6edd61c6c2cdb4ba295cf0af96.tar.gz
Merge tag 'tegra-for-3.20-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/soc
Merge "ARM: tegra: Core code changes for v3.20" from Thierry Reding: This contains a couple of preparatory patches for 64-bit support. A new feature is implemented in the power-management controller which allows it to switch off the SoC if it overheats. * tag 'tegra-for-3.20-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: soc: tegra: Add thermal reset (thermtrip) support to PMC ARM: tegra: Add PMC thermtrip programming to Jetson TK1 device tree of: Add descriptions of thermtrip properties to Tegra PMC bindings soc/tegra: pmc: Add Tegra132 support soc/tegra: fuse: Add Tegra132 support soc/tegra: fuse: Constify tegra_fuse_info structures soc/tegra: Add Tegra132 support clocksource: Build Tegra timer on 32-bit ARM only soc/tegra: pmc: restrict compilation of suspend-related support to ARM Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'Documentation/devicetree')
-rw-r--r--Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt26
1 files changed, 26 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt
index 68ac65f..2fd5051 100644
--- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt
+++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt
@@ -47,6 +47,23 @@ Required properties when nvidia,suspend-mode=<0>:
sleep mode, the warm boot code will restore some PLLs, clocks and then
bring up CPU0 for resuming the system.
+Hardware-triggered thermal reset:
+On Tegra30, Tegra114 and Tegra124, if the 'i2c-thermtrip' subnode exists,
+hardware-triggered thermal reset will be enabled.
+
+Required properties for hardware-triggered thermal reset (inside 'i2c-thermtrip'):
+- nvidia,i2c-controller-id : ID of I2C controller to send poweroff command to. Valid values are
+ described in section 9.2.148 "APBDEV_PMC_SCRATCH53_0" of the
+ Tegra K1 Technical Reference Manual.
+- nvidia,bus-addr : Bus address of the PMU on the I2C bus
+- nvidia,reg-addr : I2C register address to write poweroff command to
+- nvidia,reg-data : Poweroff command to write to PMU
+
+Optional properties for hardware-triggered thermal reset (inside 'i2c-thermtrip'):
+- nvidia,pinmux-id : Pinmux used by the hardware when issuing poweroff command.
+ Defaults to 0. Valid values are described in section 12.5.2
+ "Pinmux Support" of the Tegra4 Technical Reference Manual.
+
Example:
/ SoC dts including file
@@ -69,6 +86,15 @@ pmc@7000f400 {
/ Tegra board dts file
{
...
+ pmc@7000f400 {
+ i2c-thermtrip {
+ nvidia,i2c-controller-id = <4>;
+ nvidia,bus-addr = <0x40>;
+ nvidia,reg-addr = <0x36>;
+ nvidia,reg-data = <0x2>;
+ };
+ };
+ ...
clocks {
compatible = "simple-bus";
#address-cells = <1>;
OpenPOWER on IntegriCloud