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authorJason Cooper <jason@lakedaemon.net>2012-11-21 19:55:20 +0000
committerJason Cooper <jason@lakedaemon.net>2012-11-21 19:55:20 +0000
commitc9dc03ddbf4e71f20b78277d661388c1bc466258 (patch)
tree91cf0a398dce3c8cb484a2d8e7dc185e907e4349 /Documentation/devicetree
parent61528f4e921f23e2a095aa11f27006b347e4ee70 (diff)
parent34c93c8657935d30649e777c4aa05f74f16aa418 (diff)
downloadop-kernel-dev-c9dc03ddbf4e71f20b78277d661388c1bc466258.zip
op-kernel-dev-c9dc03ddbf4e71f20b78277d661388c1bc466258.tar.gz
Merge tag 'marvell-xor-cleanup-dt-binding-3.8' of git://github.com/MISL-EBU-System-SW/mainline-public into mvebu/everything
Marvell XOR driver cleanup and DT binding for 3.8
Diffstat (limited to 'Documentation/devicetree')
-rw-r--r--Documentation/devicetree/bindings/dma/mv-xor.txt40
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diff --git a/Documentation/devicetree/bindings/dma/mv-xor.txt b/Documentation/devicetree/bindings/dma/mv-xor.txt
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+* Marvell XOR engines
+
+Required properties:
+- compatible: Should be "marvell,orion-xor"
+- reg: Should contain registers location and length (two sets)
+ the first set is the low registers, the second set the high
+ registers for the XOR engine.
+- clocks: pointer to the reference clock
+
+The DT node must also contains sub-nodes for each XOR channel that the
+XOR engine has. Those sub-nodes have the following required
+properties:
+- interrupts: interrupt of the XOR channel
+
+And the following optional properties:
+- dmacap,memcpy to indicate that the XOR channel is capable of memcpy operations
+- dmacap,memset to indicate that the XOR channel is capable of memset operations
+- dmacap,xor to indicate that the XOR channel is capable of xor operations
+
+Example:
+
+xor@d0060900 {
+ compatible = "marvell,orion-xor";
+ reg = <0xd0060900 0x100
+ 0xd0060b00 0x100>;
+ clocks = <&coreclk 0>;
+ status = "okay";
+
+ xor00 {
+ interrupts = <51>;
+ dmacap,memcpy;
+ dmacap,xor;
+ };
+ xor01 {
+ interrupts = <52>;
+ dmacap,memcpy;
+ dmacap,xor;
+ dmacap,memset;
+ };
+};
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