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authorDaniel Thompson <daniel.thompson@linaro.org>2015-06-10 21:09:36 +0100
committerStephen Boyd <sboyd@codeaurora.org>2015-06-22 15:46:10 -0700
commit41655239eaed741ac8da066bc43c2483c78e61ec (patch)
tree221950a4486bda018384926dd8f0b777bc0f343b /Documentation/devicetree
parent2cd7b0432888ef2e1f8b54c1c6f8751e1e0e9b5e (diff)
downloadop-kernel-dev-41655239eaed741ac8da066bc43c2483c78e61ec.zip
op-kernel-dev-41655239eaed741ac8da066bc43c2483c78e61ec.tar.gz
dt-bindings: Document the STM32F4 clock bindings
This adds documentation of device tree bindings for the clock related portions of the STM32 RCC block. Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org> Acked-by: Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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+STMicroelectronics STM32 Reset and Clock Controller
+===================================================
+
+The RCC IP is both a reset and a clock controller. This documentation only
+describes the clock part.
+
+Please also refer to clock-bindings.txt in this directory for common clock
+controller binding usage.
+
+Required properties:
+- compatible: Should be "st,stm32f42xx-rcc"
+- reg: should be register base and length as documented in the
+ datasheet
+- #clock-cells: 2, device nodes should specify the clock in their "clocks"
+ property, containing a phandle to the clock device node, an index selecting
+ between gated clocks and other clocks and an index specifying the clock to
+ use.
+
+Example:
+
+ rcc: rcc@40023800 {
+ #clock-cells = <2>
+ compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
+ reg = <0x40023800 0x400>;
+ };
+
+Specifying gated clocks
+=======================
+
+The primary index must be set to 0.
+
+The secondary index is the bit number within the RCC register bank, starting
+from the first RCC clock enable register (RCC_AHB1ENR, address offset 0x30).
+
+It is calculated as: index = register_offset / 4 * 32 + bit_offset.
+Where bit_offset is the bit offset within the register (LSB is 0, MSB is 31).
+
+Example:
+
+ /* Gated clock, AHB1 bit 0 (GPIOA) */
+ ... {
+ clocks = <&rcc 0 0>
+ };
+
+ /* Gated clock, AHB2 bit 4 (CRYP) */
+ ... {
+ clocks = <&rcc 0 36>
+ };
+
+Specifying other clocks
+=======================
+
+The primary index must be set to 1.
+
+The secondary index is bound with the following magic numbers:
+
+ 0 SYSTICK
+ 1 FCLK
+
+Example:
+
+ /* Misc clock, FCLK */
+ ... {
+ clocks = <&rcc 1 1>
+ };
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