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author | Stephen Boyd <sboyd@codeaurora.org> | 2017-01-09 16:26:30 -0800 |
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committer | Stephen Boyd <sboyd@codeaurora.org> | 2017-01-09 16:26:30 -0800 |
commit | a2d6ef3a230dd48ad8c7d605784eb7814018361e (patch) | |
tree | 8e66e448cffa5419a306ac9e13b60fcae5fff862 /Documentation/devicetree | |
parent | e2d793330875d60e2c81de7a75b6bba159fef70a (diff) | |
parent | d374e6fd50880c949cdfa649f6f0c7ed2321f896 (diff) | |
download | op-kernel-dev-a2d6ef3a230dd48ad8c7d605784eb7814018361e.zip op-kernel-dev-a2d6ef3a230dd48ad8c7d605784eb7814018361e.tar.gz |
Merge branch 'clk-hi3660' into clk-next
* clk-hi3660:
clk: hisilicon: Add clock driver for hi3660 SoC
dt-bindings: Document the hi3660 clock bindings
Diffstat (limited to 'Documentation/devicetree')
-rw-r--r-- | Documentation/devicetree/bindings/clock/hi3660-clock.txt | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/hi3660-clock.txt b/Documentation/devicetree/bindings/clock/hi3660-clock.txt new file mode 100644 index 0000000..cc9b86c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/hi3660-clock.txt @@ -0,0 +1,42 @@ +* Hisilicon Hi3660 Clock Controller + +The Hi3660 clock controller generates and supplies clock to various +controllers within the Hi3660 SoC. + +Required Properties: + +- compatible: the compatible should be one of the following strings to + indicate the clock controller functionality. + + - "hisilicon,hi3660-crgctrl" + - "hisilicon,hi3660-pctrl" + - "hisilicon,hi3660-pmuctrl" + - "hisilicon,hi3660-sctrl" + - "hisilicon,hi3660-iomcu" + +- reg: physical base address of the controller and length of memory mapped + region. + +- #clock-cells: should be 1. + +Each clock is assigned an identifier and client nodes use this identifier +to specify the clock which they consume. + +All these identifier could be found in <dt-bindings/clock/hi3660-clock.h>. + +Examples: + crg_ctrl: clock-controller@fff35000 { + compatible = "hisilicon,hi3660-crgctrl", "syscon"; + reg = <0x0 0xfff35000 0x0 0x1000>; + #clock-cells = <1>; + }; + + uart0: serial@fdf02000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xfdf02000 0x0 0x1000>; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>, + <&crg_ctrl HI3660_PCLK>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; |