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author | Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> | 2013-12-17 15:37:37 +0200 |
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committer | Brian Norris <computersforpeace@gmail.com> | 2014-01-03 11:22:25 -0800 |
commit | 9ba51cff551515592c1657c509923da57b330b16 (patch) | |
tree | f86754fa08d528b1f71b8fbd55d1776a17485b6a /Documentation/devicetree | |
parent | c354ae43511702092a1ee4e62db14ba738cd85ae (diff) | |
download | op-kernel-dev-9ba51cff551515592c1657c509923da57b330b16.zip op-kernel-dev-9ba51cff551515592c1657c509923da57b330b16.tar.gz |
mtd: nand: davinci: extend description of bindings
Extend bindings for davinci_nand driver to be more clear.
This is clarification only, without semantic changes.
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by: Taras Kondratiuk <taras@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Diffstat (limited to 'Documentation/devicetree')
-rw-r--r-- | Documentation/devicetree/bindings/mtd/davinci-nand.txt | 77 |
1 files changed, 54 insertions, 23 deletions
diff --git a/Documentation/devicetree/bindings/mtd/davinci-nand.txt b/Documentation/devicetree/bindings/mtd/davinci-nand.txt index 3545ea7..d2a3fc0 100644 --- a/Documentation/devicetree/bindings/mtd/davinci-nand.txt +++ b/Documentation/devicetree/bindings/mtd/davinci-nand.txt @@ -1,36 +1,67 @@ -* Texas Instruments Davinci NAND +Device tree bindings for Texas instruments Davinci NAND controller -This file provides information, what the device node for the -davinci nand interface contain. +This file provides information, what the device node for the davinci NAND +interface contains. + +Documentation: +Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf Required properties: -- compatible: "ti,davinci-nand"; -- reg : contain 2 offset/length values: - - offset and length for the access window - - offset and length for accessing the aemif control registers -- ti,davinci-chipselect: Indicates on the davinci_nand driver which - chipselect is used for accessing the nand. + +- compatible: "ti,davinci-nand" + +- reg: Contains 2 offset/length values: + - offset and length for the access window. + - offset and length for accessing the AEMIF + control registers. + +- ti,davinci-chipselect: number of chipselect. Indicates on the + davinci_nand driver which chipselect is used + for accessing the nand. + Can be in the range [0-3]. Recommended properties : -- ti,davinci-mask-ale: mask for ale -- ti,davinci-mask-cle: mask for cle -- ti,davinci-mask-chipsel: mask for chipselect -- ti,davinci-ecc-mode: ECC mode valid values for davinci driver: - - "none" - - "soft" - - "hw" -- ti,davinci-ecc-bits: used ECC bits, currently supported 1 or 4. -- ti,davinci-nand-buswidth: buswidth 8 or 16 -- ti,davinci-nand-use-bbt: use flash based bad block table support. - -nand device bindings may contain additional sub-nodes describing -partitions of the address space. See partition.txt for more detail. + +- ti,davinci-mask-ale: mask for ALE. Needed for executing address + phase. These offset will be added to the base + address for the chip select space the NAND Flash + device is connected to. + If not set equal to 0x08. + +- ti,davinci-mask-cle: mask for CLE. Needed for executing command + phase. These offset will be added to the base + address for the chip select space the NAND Flash + device is connected to. + If not set equal to 0x10. + +- ti,davinci-mask-chipsel: mask for chipselect address. Needed to mask + addresses for given chipselect. + +- ti,davinci-ecc-mode: operation mode of the NAND ecc mode. ECC mode + valid values for davinci driver: + - "none" + - "soft" + - "hw" + +- ti,davinci-ecc-bits: used ECC bits, currently supported 1 or 4. + +- ti,davinci-nand-buswidth: buswidth 8 or 16. + +- ti,davinci-nand-use-bbt: use flash based bad block table support. OOB + identifier is saved in OOB area. + +Nand device bindings may contain additional sub-nodes describing partitions of +the address space. See partition.txt for more detail. The NAND Flash timing +values must be programmed in the chip select’s node of AEMIF +memory-controller (see Documentation/devicetree/bindings/memory-controllers/ +davinci-aemif.txt). Example(da850 EVM ): + nand_cs3@62000000 { compatible = "ti,davinci-nand"; reg = <0x62000000 0x807ff - 0x68000000 0x8000>; + 0x68000000 0x8000>; ti,davinci-chipselect = <1>; ti,davinci-mask-ale = <0>; ti,davinci-mask-cle = <0>; |