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| author | Matt Weber <matthew.weber@rockwellcollins.com> | 2017-06-22 15:00:33 -0500 |
|---|---|---|
| committer | Wolfram Sang <wsa@the-dreams.de> | 2017-06-23 20:56:21 +0200 |
| commit | 8064c616984eaa015f018dba595d78cd24a0cc8c (patch) | |
| tree | f5786d9aac081c10a277b5d1a7c7060f9c5ea181 /Documentation/devicetree | |
| parent | 9615a01f71ca02858f5265b1b545280758562aa2 (diff) | |
| download | op-kernel-dev-8064c616984eaa015f018dba595d78cd24a0cc8c.zip op-kernel-dev-8064c616984eaa015f018dba595d78cd24a0cc8c.tar.gz | |
i2c: cadance: fix ctrl/addr reg write order
The driver was clearing the hold bit in the control register before
writing to the address register which resulted in a stop condition
being generated rather than a repeated start.
This issue was only observed when a system was running much
slower than a normal processor would execute. The IP data sheet
mentions a ordering of writing to the address register before
clearing the hold.
Fixes: df8eb5691c4 ("i2c: Add driver for Cadence I2C controller")
Signed-off-by: John Linn <john.linn@xilinx.com>
Signed-off-by: Paresh Chaudhary <paresh.chaudhary@rockwellcollins.com>
Signed-off-by: Matthew Weber <matthew.weber@rockwellcollins.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Diffstat (limited to 'Documentation/devicetree')
0 files changed, 0 insertions, 0 deletions
