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authorLucas Stach <l.stach@pengutronix.de>2017-03-08 12:13:15 +0100
committerPhilipp Zabel <p.zabel@pengutronix.de>2017-03-15 15:42:36 +0100
commit63863d43e8f98691a714673991884732db8c8487 (patch)
treeb8080cca75f97780b0f5b4a12840ba4182481bcb /Documentation/devicetree
parentd2a34232580a5d2c9f58baa5270836c5c9ab83ba (diff)
downloadop-kernel-dev-63863d43e8f98691a714673991884732db8c8487.zip
op-kernel-dev-63863d43e8f98691a714673991884732db8c8487.tar.gz
gpu: ipu-v3: add DT binding for the Prefetch Resolve Gasket
This adds the the devicetree binding for the Prefetch Resolve Gasket, as found on i.MX6 QuadPlus. The PRG is fairly simple in that it only has a configuration register range and two clocks, one for the AHB slave port and one for the AXI ports and the functional units. The PRE connections need to be described in the DT, as the PRE<->PRG assignment is a mix between fixed and muxable connections. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Diffstat (limited to 'Documentation/devicetree')
-rw-r--r--Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt25
1 files changed, 25 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt b/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt
index 70ae533..62eb637 100644
--- a/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt
+++ b/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt
@@ -79,6 +79,31 @@ pre@21c8000 {
fsl,iram = <&ocram2>;
};
+Freescale i.MX PRG (Prefetch Resolve Gasket)
+============================================
+
+Required properties:
+- compatible: should be "fsl,imx6qp-prg"
+- reg: should be register base and length as documented in the
+ datasheet
+- clocks : phandles to the PRG ipg and axi clock inputs, as described
+ in Documentation/devicetree/bindings/clock/clock-bindings.txt and
+ Documentation/devicetree/bindings/clock/imx6q-clock.txt.
+- clock-names: should be "ipg" and "axi"
+- fsl,pres: phandles to the PRE units attached to this PRG, with the fixed
+ PRE as the first entry and the muxable PREs following.
+
+example:
+
+prg@21cc000 {
+ compatible = "fsl,imx6qp-prg";
+ reg = <0x021cc000 0x1000>;
+ clocks = <&clks IMX6QDL_CLK_PRG0_APB>,
+ <&clks IMX6QDL_CLK_PRG0_AXI>;
+ clock-names = "ipg", "axi";
+ fsl,pres = <&pre1>, <&pre2>, <&pre3>;
+};
+
Parallel display support
========================
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