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authorDipen Dudhat <Dipen.Dudhat@freescale.com>2011-05-19 12:08:23 +0530
committerKumar Gala <galak@kernel.crashing.org>2011-05-19 01:45:07 -0500
commitbbfff72ee3e76bd4712b87386af00bfe97114bc9 (patch)
tree7433be01b541d2ae506ec48f93adf302dcc2d32e /Documentation/devicetree/bindings
parent41cd08560bbf8371bbd00e783e992b0dc7e7c83d (diff)
downloadop-kernel-dev-bbfff72ee3e76bd4712b87386af00bfe97114bc9.zip
op-kernel-dev-bbfff72ee3e76bd4712b87386af00bfe97114bc9.tar.gz
powerpc: Integrated Flash controller device tree bindings
Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> Acked-By: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'Documentation/devicetree/bindings')
-rw-r--r--Documentation/devicetree/bindings/powerpc/fsl/ifc.txt76
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diff --git a/Documentation/devicetree/bindings/powerpc/fsl/ifc.txt b/Documentation/devicetree/bindings/powerpc/fsl/ifc.txt
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+Integrated Flash Controller
+
+Properties:
+- name : Should be ifc
+- compatible : should contain "fsl,ifc". The version of the integrated
+ flash controller can be found in the IFC_REV register at
+ offset zero.
+
+- #address-cells : Should be either two or three. The first cell is the
+ chipselect number, and the remaining cells are the
+ offset into the chipselect.
+- #size-cells : Either one or two, depending on how large each chipselect
+ can be.
+- reg : Offset and length of the register set for the device
+- interrupts : IFC has two interrupts. The first one is the "common"
+ interrupt(CM_EVTER_STAT), and second is the NAND interrupt
+ (NAND_EVTER_STAT).
+
+- ranges : Each range corresponds to a single chipselect, and covers
+ the entire access window as configured.
+
+Child device nodes describe the devices connected to IFC such as NOR (e.g.
+cfi-flash) and NAND (fsl,ifc-nand). There might be board specific devices
+like FPGAs, CPLDs, etc.
+
+Example:
+
+ ifc@ffe1e000 {
+ compatible = "fsl,ifc", "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ reg = <0x0 0xffe1e000 0 0x2000>;
+ interrupts = <16 2 19 2>;
+
+ /* NOR, NAND Flashes and CPLD on board */
+ ranges = <0x0 0x0 0x0 0xee000000 0x02000000
+ 0x1 0x0 0x0 0xffa00000 0x00010000
+ 0x3 0x0 0x0 0xffb00000 0x00020000>;
+
+ flash@0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x0 0x0 0x2000000>;
+ bank-width = <2>;
+ device-width = <1>;
+
+ partition@0 {
+ /* 32MB for user data */
+ reg = <0x0 0x02000000>;
+ label = "NOR Data";
+ };
+ };
+
+ flash@1,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,ifc-nand";
+ reg = <0x1 0x0 0x10000>;
+
+ partition@0 {
+ /* This location must not be altered */
+ /* 1MB for u-boot Bootloader Image */
+ reg = <0x0 0x00100000>;
+ label = "NAND U-Boot Image";
+ read-only;
+ };
+ };
+
+ cpld@3,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,p1010rdb-cpld";
+ reg = <0x3 0x0 0x000001f>;
+ };
+ };
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