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author | Laxman Dewangan <ldewangan@nvidia.com> | 2013-01-08 16:27:44 +0530 |
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committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2013-01-15 22:15:17 -0800 |
commit | e9ea096dd2259454e0d09d0b0445fe8f0117add4 (patch) | |
tree | 7feeb18200f00e0a9c7f6deba1aa04a801914d61 /Documentation/devicetree/bindings/serial | |
parent | 42d34191545be343909417dd05db799686f2e48e (diff) | |
download | op-kernel-dev-e9ea096dd2259454e0d09d0b0445fe8f0117add4.zip op-kernel-dev-e9ea096dd2259454e0d09d0b0445fe8f0117add4.tar.gz |
serial: tegra: add serial driver
NVIDIA's Tegra has multiple UART controller which supports:
- APB DMA based controller fifo read/write.
- End Of Data interrupt in incoming data to know whether end
of frame achieve or not.
- HW controlled RTS and CTS flow control to reduce SW overhead.
Add serial driver to use all above feature.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Acked-by: Alan Cox <alan@linux.intel.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'Documentation/devicetree/bindings/serial')
-rw-r--r-- | Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt b/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt new file mode 100644 index 0000000..392a449 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt @@ -0,0 +1,24 @@ +NVIDIA Tegra20/Tegra30 high speed (DMA based) UART controller driver. + +Required properties: +- compatible : should be "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart". +- reg: Should contain UART controller registers location and length. +- interrupts: Should contain UART controller interrupts. +- nvidia,dma-request-selector : The Tegra DMA controller's phandle and + request selector for this UART controller. + +Optional properties: +- nvidia,enable-modem-interrupt: Enable modem interrupts. Should be enable + only if all 8 lines of UART controller are pinmuxed. + +Example: + +serial@70006000 { + compatible = "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart"; + reg = <0x70006000 0x40>; + reg-shift = <2>; + interrupts = <0 36 0x04>; + nvidia,dma-request-selector = <&apbdma 8>; + nvidia,enable-modem-interrupt; + status = "disabled"; +}; |