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authorShawn Lin <shawn.lin@rock-chips.com>2016-09-01 15:44:53 +0800
committerKishon Vijay Abraham I <kishon@ti.com>2016-09-10 16:48:32 +0530
commitb11c821532b53976ff8af1b9c98d114facdfadcb (patch)
tree1abfff898183360e460a21ea888a45598dcd0777 /Documentation/devicetree/bindings/phy
parent0e08d2a727e68bbe426457dc61ec11a5c6a76ed6 (diff)
downloadop-kernel-dev-b11c821532b53976ff8af1b9c98d114facdfadcb.zip
op-kernel-dev-b11c821532b53976ff8af1b9c98d114facdfadcb.tar.gz
Documentation: bindings: add dt documentation for Rockchip PCIe PHY
This patch adds a binding that describes the Rockchip PCIe PHY found on Rockchip SoCs PCIe interface. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Diffstat (limited to 'Documentation/devicetree/bindings/phy')
-rw-r--r--Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt31
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diff --git a/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
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+++ b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
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+Rockchip PCIE PHY
+-----------------------
+
+Required properties:
+ - compatible: rockchip,rk3399-pcie-phy
+ - #phy-cells: must be 0
+ - clocks: Must contain an entry in clock-names.
+ See ../clocks/clock-bindings.txt for details.
+ - clock-names: Must be "refclk"
+ - resets: Must contain an entry in reset-names.
+ See ../reset/reset.txt for details.
+ - reset-names: Must be "phy"
+
+Example:
+
+grf: syscon@ff770000 {
+ compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ...
+
+ pcie_phy: pcie-phy {
+ compatible = "rockchip,rk3399-pcie-phy";
+ #phy-cells = <0>;
+ clocks = <&cru SCLK_PCIEPHY_REF>;
+ clock-names = "refclk";
+ resets = <&cru SRST_PCIEPHY>;
+ reset-names = "phy";
+ };
+};
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