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author | Jaewon Kim <jaewon02.kim@samsung.com> | 2015-03-12 19:11:13 +0900 |
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committer | Kishon Vijay Abraham I <kishon@ti.com> | 2015-03-26 05:06:10 +0530 |
commit | 2be608561abfcceda4b35b71a0c1ec5088bb39b9 (patch) | |
tree | 78bebecf685019084e49f905d42ff577516209ed /Documentation/devicetree/bindings/phy | |
parent | d89a7f69d69409ffafad7affc1cc3085d2cd0dd8 (diff) | |
download | op-kernel-dev-2be608561abfcceda4b35b71a0c1ec5088bb39b9.zip op-kernel-dev-2be608561abfcceda4b35b71a0c1ec5088bb39b9.tar.gz |
phy: exynos5-usbdrd: Add to support for Exynos5433 SoC
This patch adds driver data to support for Exynos5433 SoC.
The Exynos5433 has one USB3.0 Host and USB3.0 DRD(Dual Role Device).
Exynos5433 is simplar to Eyxnos7 but Exynos5433 have
one more USB3.0 Host controller.
Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Diffstat (limited to 'Documentation/devicetree/bindings/phy')
-rw-r--r-- | Documentation/devicetree/bindings/phy/samsung-phy.txt | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt b/Documentation/devicetree/bindings/phy/samsung-phy.txt index 91e38cf..60c6f2a 100644 --- a/Documentation/devicetree/bindings/phy/samsung-phy.txt +++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt @@ -128,6 +128,7 @@ Required properties: - compatible : Should be set to one of the following supported values: - "samsung,exynos5250-usbdrd-phy" - for exynos5250 SoC, - "samsung,exynos5420-usbdrd-phy" - for exynos5420 SoC. + - "samsung,exynos5433-usbdrd-phy" - for exynos5433 SoC. - "samsung,exynos7-usbdrd-phy" - for exynos7 SoC. - reg : Register offset and length of USB DRD PHY register set; - clocks: Clock IDs array as required by the controller @@ -139,7 +140,7 @@ Required properties: PHY operations, associated by phy name. It is used to determine bit values for clock settings register. For Exynos5420 this is given as 'sclk_usbphy30' in CMU. - - optional clocks: Exynos7 SoC has now following additional + - optional clocks: Exynos5433 & Exynos7 SoC has now following additional gate clocks available: - phy_pipe: for PIPE3 phy - phy_utmi: for UTMI+ phy |