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authorNeil Armstrong <narmstrong@baylibre.com>2016-10-20 10:49:01 +0200
committerBoris Brezillon <boris.brezillon@free-electrons.com>2016-10-22 14:24:21 +0200
commit668592492409498afc277da41e84799e1d2255c2 (patch)
tree2e7bd5f75373ac31657dc5c316f0dd76f6e5de1b /Documentation/devicetree/bindings/mtd
parent6ac18a4859b3a7d55874bed2ebe6d704b7926a10 (diff)
downloadop-kernel-dev-668592492409498afc277da41e84799e1d2255c2.zip
op-kernel-dev-668592492409498afc277da41e84799e1d2255c2.tar.gz
mtd: nand: Add OX820 NAND Support
Add NAND driver to support the Oxford Semiconductor OX820 NAND Controller. This is a simple memory mapped NAND controller with single chip select and software ECC. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
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diff --git a/Documentation/devicetree/bindings/mtd/oxnas-nand.txt b/Documentation/devicetree/bindings/mtd/oxnas-nand.txt
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+* Oxford Semiconductor OXNAS NAND Controller
+
+Please refer to nand.txt for generic information regarding MTD NAND bindings.
+
+Required properties:
+ - compatible: "oxsemi,ox820-nand"
+ - reg: Base address and length for NAND mapped memory.
+
+Optional Properties:
+ - clocks: phandle to the NAND gate clock if needed.
+ - resets: phandle to the NAND reset control if needed.
+
+Example:
+
+nandc: nand-controller@41000000 {
+ compatible = "oxsemi,ox820-nand";
+ reg = <0x41000000 0x100000>;
+ clocks = <&stdclk CLK_820_NAND>;
+ resets = <&reset RESET_NAND>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ nand@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ nand-ecc-mode = "soft";
+ nand-ecc-algo = "hamming";
+
+ partition@0 {
+ label = "boot";
+ reg = <0x00000000 0x00e00000>;
+ read-only;
+ };
+
+ partition@e00000 {
+ label = "ubi";
+ reg = <0x00e00000 0x07200000>;
+ };
+ };
+};
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