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authorWill Deacon <will.deacon@arm.com>2015-05-27 17:25:58 +0100
committerJoerg Roedel <jroedel@suse.de>2015-05-29 11:12:01 +0200
commita73e528ab1499505c29e14091b19cb041e20e038 (patch)
treeb326afcff99ed4767d3cae63cc5f1b8785dd9807 /Documentation/devicetree/bindings/iommu
parente3ce0c940e02e4d9d09c1c1377f80d9e90a893a0 (diff)
downloadop-kernel-dev-a73e528ab1499505c29e14091b19cb041e20e038.zip
op-kernel-dev-a73e528ab1499505c29e14091b19cb041e20e038.tar.gz
Documentation: dt-bindings: Add device-tree binding for ARM SMMUv3 IOMMU
This patch adds device-tree bindings for ARM SMMUv3 IOMMU devices. Cc: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
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+* ARM SMMUv3 Architecture Implementation
+
+The SMMUv3 architecture is a significant deparature from previous
+revisions, replacing the MMIO register interface with in-memory command
+and event queues and adding support for the ATS and PRI components of
+the PCIe specification.
+
+** SMMUv3 required properties:
+
+- compatible : Should include:
+
+ * "arm,smmu-v3" for any SMMUv3 compliant
+ implementation. This entry should be last in the
+ compatible list.
+
+- reg : Base address and size of the SMMU.
+
+- interrupts : Non-secure interrupt list describing the wired
+ interrupt sources corresponding to entries in
+ interrupt-names. If no wired interrupts are
+ present then this property may be omitted.
+
+- interrupt-names : When the interrupts property is present, should
+ include the following:
+ * "eventq" - Event Queue not empty
+ * "priq" - PRI Queue not empty
+ * "cmdq-sync" - CMD_SYNC complete
+ * "gerror" - Global Error activated
+
+** SMMUv3 optional properties:
+
+- dma-coherent : Present if DMA operations made by the SMMU (page
+ table walks, stream table accesses etc) are cache
+ coherent with the CPU.
+
+ NOTE: this only applies to the SMMU itself, not
+ masters connected upstream of the SMMU.
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