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author | Michael Turquette <mturquette@baylibre.com> | 2016-01-04 16:16:45 -0800 |
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committer | Michael Turquette <mturquette@baylibre.com> | 2016-01-04 16:16:45 -0800 |
commit | b360ada3f1534a37b264274cad55932d2a214ec3 (patch) | |
tree | 052ded4d0172924ee55d3d4e2c3ea18146e3b629 /Documentation/devicetree/bindings/clock | |
parent | 7ed88aa2efa5422f9d93fd99f2a01c56e28a7409 (diff) | |
parent | 2d7f61f37731f635af47615a8a331ffe7f884934 (diff) | |
download | op-kernel-dev-b360ada3f1534a37b264274cad55932d2a214ec3.zip op-kernel-dev-b360ada3f1534a37b264274cad55932d2a214ec3.tar.gz |
Merge tag 'tegra-for-4.5-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-next
clk: tegra: Changes for v4.5-rc1
This set of changes adds support for the Tegra210 SoC and contains a
couple fixes and cleanups.
Diffstat (limited to 'Documentation/devicetree/bindings/clock')
-rw-r--r-- | Documentation/devicetree/bindings/clock/nvidia,tegra210-car.txt | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra210-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra210-car.txt new file mode 100644 index 0000000..26f237f --- /dev/null +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra210-car.txt @@ -0,0 +1,56 @@ +NVIDIA Tegra210 Clock And Reset Controller + +This binding uses the common clock binding: +Documentation/devicetree/bindings/clock/clock-bindings.txt + +The CAR (Clock And Reset) Controller on Tegra is the HW module responsible +for muxing and gating Tegra's clocks, and setting their rates. + +Required properties : +- compatible : Should be "nvidia,tegra210-car" +- reg : Should contain CAR registers location and length +- clocks : Should contain phandle and clock specifiers for two clocks: + the 32 KHz "32k_in". +- #clock-cells : Should be 1. + In clock consumers, this cell represents the clock ID exposed by the + CAR. The assignments may be found in header file + <dt-bindings/clock/tegra210-car.h>. +- #reset-cells : Should be 1. + In clock consumers, this cell represents the bit number in the CAR's + array of CLK_RST_CONTROLLER_RST_DEVICES_* registers. + +Example SoC include file: + +/ { + tegra_car: clock { + compatible = "nvidia,tegra210-car"; + reg = <0x60006000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + usb@c5004000 { + clocks = <&tegra_car TEGRA210_CLK_USB2>; + }; +}; + +Example board file: + +/ { + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk_32k: clock@1 { + compatible = "fixed-clock"; + reg = <1>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + + &tegra_car { + clocks = <&clk_32k>; + }; +}; |