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authorArnd Bergmann <arnd@arndb.de>2015-12-16 00:04:26 +0100
committerArnd Bergmann <arnd@arndb.de>2015-12-16 00:04:26 +0100
commit8ea1c981b6303904a2d92102f903843bda9df58c (patch)
tree9cef253e8f5d6b4279eb867f58a1defb81d7b193 /Documentation/devicetree/bindings/clock
parentee5d89239500de9eff188c26375c3512d8ac7f6f (diff)
parentacde758b31f33d1599a07930b8c0ea082157cf70 (diff)
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Merge tag 'realview-base-armsoc-2-tag' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into next/dt
Merge "Realview DT files" from Linus Walleij: The device tree changes for the continued RealView DT support. * tag 'realview-base-armsoc-2-tag' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator: ARM: realview: add device tree for PB11MPCore clk: add ARM syscon ICST device tree bindings ARM: add DT bindings for the ARM11MPCore CPU cluster
Diffstat (limited to 'Documentation/devicetree/bindings/clock')
-rw-r--r--Documentation/devicetree/bindings/clock/arm-syscon-icst.txt40
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diff --git a/Documentation/devicetree/bindings/clock/arm-syscon-icst.txt b/Documentation/devicetree/bindings/clock/arm-syscon-icst.txt
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+ARM System Controller ICST clocks
+
+The ICS525 and ICS307 oscillators are produced by Integrated Devices
+Technology (IDT). ARM integrated these oscillators deeply into their
+reference designs by adding special control registers that manage such
+oscillators to their system controllers.
+
+The ARM system controller contains logic to serialize and initialize
+an ICST clock request after a write to the 32 bit register at an offset
+into the system controller. Furthermore, to even be able to alter one of
+these frequencies, the system controller must first be unlocked by
+writing a special token to another offset in the system controller.
+
+The ICST oscillator must be provided inside a system controller node.
+
+Required properties:
+- lock-offset: the offset address into the system controller where the
+ unlocking register is located
+- vco-offset: the offset address into the system controller where the
+ ICST control register is located (even 32 bit address)
+- compatible: must be one of "arm,syscon-icst525" or "arm,syscon-icst307"
+- #clock-cells: must be <0>
+- clocks: parent clock, since the ICST needs a parent clock to derive its
+ frequency from, this attribute is compulsory.
+
+Example:
+
+syscon: syscon@10000000 {
+ compatible = "syscon";
+ reg = <0x10000000 0x1000>;
+
+ oscclk0: osc0@0c {
+ compatible = "arm,syscon-icst307";
+ #clock-cells = <0>;
+ lock-offset = <0x20>;
+ vco-offset = <0x0c>;
+ clocks = <&xtal24mhz>;
+ };
+ (...)
+};
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