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author | Dinh Nguyen <dinguyen@altera.com> | 2014-04-16 15:05:15 -0500 |
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committer | Dinh Nguyen <dinguyen@altera.com> | 2014-05-05 22:33:18 -0500 |
commit | 8cb289ed60668d3350dda5aa19b4fa1dce1c07f1 (patch) | |
tree | 2c254d8089be3b05be5db6db16f07d23ab11986d /Documentation/devicetree/bindings/clock | |
parent | 16fb4f8bd59e0e954991f624bcc53dad2052ef0d (diff) | |
download | op-kernel-dev-8cb289ed60668d3350dda5aa19b4fa1dce1c07f1.zip op-kernel-dev-8cb289ed60668d3350dda5aa19b4fa1dce1c07f1.tar.gz |
ARM: socfpga: dts: Add div-reg to the main_pll clocks
The mpu_clk, main_clk, and dbg_base_clk outputs from the main PLL go through a
pre-divider. Update socfpga.dtsi to represent those dividers for these
clocks.
Re-use the "div-reg" property that was used for the socfpga-gate-clock as this
is the same thing. Also update the documentation.
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Diffstat (limited to 'Documentation/devicetree/bindings/clock')
-rw-r--r-- | Documentation/devicetree/bindings/clock/altr_socfpga.txt | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/clock/altr_socfpga.txt b/Documentation/devicetree/bindings/clock/altr_socfpga.txt index 5dfd145..f72e80e 100644 --- a/Documentation/devicetree/bindings/clock/altr_socfpga.txt +++ b/Documentation/devicetree/bindings/clock/altr_socfpga.txt @@ -21,8 +21,8 @@ Optional properties: - fixed-divider : If clocks have a fixed divider value, use this property. - clk-gate : For "socfpga-gate-clk", clk-gate contains the gating register and the bit index. -- div-reg : For "socfpga-gate-clk", div-reg contains the divider register, bit shift, - and width. +- div-reg : For "socfpga-gate-clk" and "socfpga-periph-clock", div-reg contains + the divider register, bit shift, and width. - clk-phase : For the sdmmc_clk, contains the value of the clock phase that controls the SDMMC CIU clock. The first value is the clk_sample(smpsel), and the second value is the cclk_in_drv(drvsel). The clk-phase is used to enable the correct |