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author | Simon Horman <horms+renesas@verge.net.au> | 2014-04-18 08:05:50 +0900 |
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committer | Mike Turquette <mturquette@linaro.org> | 2014-05-12 23:07:40 -0700 |
commit | 7b42a997bfb93c6ae0709f34ec8e2860757804b5 (patch) | |
tree | 99b7c320189bd40b6b3530ea3dcb1279a7eb23bc /Documentation/devicetree/bindings/clock | |
parent | a854aea24c09599be75e1456f9cbe2ba78320a7b (diff) | |
download | op-kernel-dev-7b42a997bfb93c6ae0709f34ec8e2860757804b5.zip op-kernel-dev-7b42a997bfb93c6ae0709f34ec8e2860757804b5.tar.gz |
clk: shmobile: r8a7779: Add clocks support
The R8A7779 SoC has several clocks that are too custom to be supported in a
generic driver. Those clocks are all fixed rate clocks with multiplier and
divisor set according to boot mode configuration.
Based on work for R-Car Gen2 SoCs by Laurent Pinchart.
Cc: devicetree@vger.kernel.org
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'Documentation/devicetree/bindings/clock')
-rw-r--r-- | Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt new file mode 100644 index 0000000..ed3c8cb --- /dev/null +++ b/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt @@ -0,0 +1,27 @@ +* Renesas R8A7779 Clock Pulse Generator (CPG) + +The CPG generates core clocks for the R8A7779. It includes one PLL and +several fixed ratio dividers + +Required Properties: + + - compatible: Must be "renesas,r8a7779-cpg-clocks" + - reg: Base address and length of the memory resource used by the CPG + + - clocks: Reference to the parent clock + - #clock-cells: Must be 1 + - clock-output-names: The names of the clocks. Supported clocks are "plla", + "z", "zs", "s", "s1", "p", "b", "out". + + +Example +------- + + cpg_clocks: cpg_clocks@ffc80000 { + compatible = "renesas,r8a7779-cpg-clocks"; + reg = <0 0xffc80000 0 0x30>; + clocks = <&extal_clk>; + #clock-cells = <1>; + clock-output-names = "plla", "z", "zs", "s", "s1", "p", + "b", "out"; + }; |