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author | Lars-Peter Clausen <lars@metafoo.de> | 2013-03-11 16:22:29 +0100 |
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committer | Mike Turquette <mturquette@linaro.org> | 2013-03-19 17:20:30 -0700 |
commit | 0e646c52cf0ee186ec50b41c4db8cf81500c8dd1 (patch) | |
tree | af5089cddec769ba2cfcd8f846dfc156bc39481a /Documentation/devicetree/bindings/clock/axi-clkgen.txt | |
parent | 2850985f7749abca7fc374a438bc0126ca28c9c4 (diff) | |
download | op-kernel-dev-0e646c52cf0ee186ec50b41c4db8cf81500c8dd1.zip op-kernel-dev-0e646c52cf0ee186ec50b41c4db8cf81500c8dd1.tar.gz |
clk: Add axi-clkgen driver
This driver adds support for the AXI clkgen pcore to the common clock framework.
The AXI clkgen pcore is a AXI front-end to the MMCM_ADV frequency synthesizer
commonly found in Xilinx FPGAs.
The AXI clkgen pcore is used in Analog Devices' reference designs targeting
Xilinx FPGAs.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'Documentation/devicetree/bindings/clock/axi-clkgen.txt')
-rw-r--r-- | Documentation/devicetree/bindings/clock/axi-clkgen.txt | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/axi-clkgen.txt b/Documentation/devicetree/bindings/clock/axi-clkgen.txt new file mode 100644 index 0000000..028b493 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/axi-clkgen.txt @@ -0,0 +1,22 @@ +Binding for the axi-clkgen clock generator + +This binding uses the common clock binding[1]. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt + +Required properties: +- compatible : shall be "adi,axi-clkgen". +- #clock-cells : from common clock binding; Should always be set to 0. +- reg : Address and length of the axi-clkgen register set. +- clocks : Phandle and clock specifier for the parent clock. + +Optional properties: +- clock-output-names : From common clock binding. + +Example: + clock@0xff000000 { + compatible = "adi,axi-clkgen"; + #clock-cells = <0>; + reg = <0xff000000 0x1000>; + clocks = <&osc 1>; + }; |