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authorThierry Reding <treding@nvidia.com>2018-04-27 11:18:14 +0200
committerRob Herring <robh@kernel.org>2018-05-01 11:29:16 -0500
commited0d3a6af53501fdd4b03d9162ceb9ee4e38ec24 (patch)
tree92bcc4f1ad97ce696366f6347b2c1634811428bc /Documentation/devicetree/bindings/arm
parente0359c461d8cfdef3fc9b02efda2352dd1de8198 (diff)
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dt-bindings: Relocate Tegra20 memory controller bindings
Move the device tree bindings for the Tegra20 memory controller to the same location as the Tegra30 (and later) memory controller bindings. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Rob Herring <robh@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/arm')
-rw-r--r--Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-mc.txt16
1 files changed, 0 insertions, 16 deletions
diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-mc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-mc.txt
deleted file mode 100644
index f9632ba..0000000
--- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-mc.txt
+++ /dev/null
@@ -1,16 +0,0 @@
-NVIDIA Tegra20 MC(Memory Controller)
-
-Required properties:
-- compatible : "nvidia,tegra20-mc"
-- reg : Should contain 2 register ranges(address and length); see the
- example below. Note that the MC registers are interleaved with the
- GART registers, and hence must be represented as multiple ranges.
-- interrupts : Should contain MC General interrupt.
-
-Example:
- memory-controller@7000f000 {
- compatible = "nvidia,tegra20-mc";
- reg = <0x7000f000 0x024
- 0x7000f03c 0x3c4>;
- interrupts = <0 77 0x04>;
- };
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