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authorAntoine Tenart <antoine.tenart@free-electrons.com>2014-05-05 07:27:28 +0200
committerSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>2014-05-19 23:02:30 +0200
commite9673a752897c2127e5aefd4663016bca817a0fe (patch)
tree6e90156fb323183c8324cc99f81436dd9be4dcf1 /Documentation/devicetree/bindings/arm
parent414dcf8f30fb966490a08c6f2bb581a745395309 (diff)
downloadop-kernel-dev-e9673a752897c2127e5aefd4663016bca817a0fe.zip
op-kernel-dev-e9673a752897c2127e5aefd4663016bca817a0fe.tar.gz
dt-binding: ARM: add pinctrl binding docs for Marvell Berlin2 SoCs
Add pin control binding documentation to the SoC binding documentaion as pinctrl is part of chip/system control registers. The documentation also explains how to configure this group based controller. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Diffstat (limited to 'Documentation/devicetree/bindings/arm')
-rw-r--r--Documentation/devicetree/bindings/arm/marvell,berlin.txt54
1 files changed, 54 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/marvell,berlin.txt b/Documentation/devicetree/bindings/arm/marvell,berlin.txt
index 744a7ea..94013a9 100644
--- a/Documentation/devicetree/bindings/arm/marvell,berlin.txt
+++ b/Documentation/devicetree/bindings/arm/marvell,berlin.txt
@@ -41,6 +41,18 @@ Required properties:
BG2/BG2CD: chip control register set
BG2Q: chip control register set and cpu pll registers
+* Marvell Berlin2 system control binding
+
+Marvell Berlin SoCs have a system control register set providing several
+individual registers dealing with pinmux, padmux, and reset.
+
+Required properties:
+- compatible: should be one of
+ "marvell,berlin2-system-ctrl" for BG2
+ "marvell,berlin2cd-system-ctrl" for BG2CD
+ "marvell,berlin2q-system-ctrl" for BG2Q
+- reg: address and length of the system control register set
+
* Clock provider binding
As clock related registers are spread among the chip control registers, the
@@ -61,6 +73,23 @@ Clocks provided by core clocks shall be referenced by a clock specifier
indexing one of the provided clocks. Refer to dt-bindings/clock/berlin<soc>.h
for the corresponding index mapping.
+* Pin controller binding
+
+Pin control registers are part of both register sets, chip control and system
+control. The pins controlled are organized in groups, so no actual pin
+information is needed.
+
+A pin-controller node should contain subnodes representing the pin group
+configurations, one per function. Each subnode has the group name and the muxing
+function used.
+
+Be aware the Marvell Berlin datasheets use the keyword 'mode' for what is called
+a 'function' in the pin-controller subsystem.
+
+Required subnode-properties:
+- groups: a list of strings describing the group names.
+- function: a string describing the function used to mux the groups.
+
Example:
chip: chip-control@ea0000 {
@@ -69,4 +98,29 @@ chip: chip-control@ea0000 {
reg = <0xea0000 0x400>;
clocks = <&refclk>, <&externaldev 0>;
clock-names = "refclk", "video_ext0";
+
+ spi1_pmux: spi1-pmux {
+ groups = "G0";
+ function = "spi1";
+ };
+};
+
+sysctrl: system-controller@d000 {
+ compatible = "marvell,berlin2-system-ctrl";
+ reg = <0xd000 0x100>;
+
+ uart0_pmux: uart0-pmux {
+ groups = "GSM4";
+ function = "uart0";
+ };
+
+ uart1_pmux: uart1-pmux {
+ groups = "GSM5";
+ function = "uart1";
+ };
+
+ uart2_pmux: uart2-pmux {
+ groups = "GSM3";
+ function = "uart2";
+ };
};
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