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author | Linus Walleij <linus.walleij@linaro.org> | 2015-05-19 10:55:19 -0600 |
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committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2015-05-24 11:12:08 -0700 |
commit | 70dd9d2f0af0e9ebe1c508dfa9a2ba0524f56cd5 (patch) | |
tree | 61cfd36b41563412230f247bb4563bd76a0ea90f /Documentation/devicetree/bindings/arm/coresight.txt | |
parent | 9875cd9ce2b5363528b5518ddd3e3b670da74161 (diff) | |
download | op-kernel-dev-70dd9d2f0af0e9ebe1c508dfa9a2ba0524f56cd5.zip op-kernel-dev-70dd9d2f0af0e9ebe1c508dfa9a2ba0524f56cd5.tar.gz |
coresight: document the bindings for the ATCLK
Put in a blurb in the device tree bindings indicating that
coresight blocks may have an optional ATCLK.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'Documentation/devicetree/bindings/arm/coresight.txt')
-rw-r--r-- | Documentation/devicetree/bindings/arm/coresight.txt | 13 |
1 files changed, 8 insertions, 5 deletions
diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt index 88602b7..8711c10 100644 --- a/Documentation/devicetree/bindings/arm/coresight.txt +++ b/Documentation/devicetree/bindings/arm/coresight.txt @@ -21,11 +21,14 @@ its hardware characteristcs. * reg: physical base address and length of the register set(s) of the component. - * clocks: the clock associated to this component. - - * clock-names: the name of the clock as referenced by the code. - Since we are using the AMBA framework, the name should be - "apb_pclk". + * clocks: the clocks associated to this component. + + * clock-names: the name of the clocks referenced by the code. + Since we are using the AMBA framework, the name of the clock + providing the interconnect should be "apb_pclk", and some + coresight blocks also have an additional clock "atclk", which + clocks the core of that coresight component. The latter clock + is optional. * port or ports: The representation of the component's port layout using the generic DT graph presentation found in |