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author | Ingo Molnar <mingo@elte.hu> | 2008-07-31 18:43:41 +0200 |
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committer | Ingo Molnar <mingo@elte.hu> | 2008-07-31 18:43:41 +0200 |
commit | 85e9ca333d03fbd56b9e123c8456f0d98e20faad (patch) | |
tree | 7bb15ada5f536950efa23ad60ea9eea60380ca1c /Documentation/DMA-attributes.txt | |
parent | a300bec952127d9a15e666b391bb35c9aecb3002 (diff) | |
parent | 6e86841d05f371b5b9b86ce76c02aaee83352298 (diff) | |
download | op-kernel-dev-85e9ca333d03fbd56b9e123c8456f0d98e20faad.zip op-kernel-dev-85e9ca333d03fbd56b9e123c8456f0d98e20faad.tar.gz |
Merge branch 'linus' into timers/hpet
Diffstat (limited to 'Documentation/DMA-attributes.txt')
-rw-r--r-- | Documentation/DMA-attributes.txt | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/Documentation/DMA-attributes.txt b/Documentation/DMA-attributes.txt index 6d772f8..b768cc0 100644 --- a/Documentation/DMA-attributes.txt +++ b/Documentation/DMA-attributes.txt @@ -22,3 +22,12 @@ ready and available in memory. The DMA of the "completion indication" could race with data DMA. Mapping the memory used for completion indications with DMA_ATTR_WRITE_BARRIER would prevent the race. +DMA_ATTR_WEAK_ORDERING +---------------------- + +DMA_ATTR_WEAK_ORDERING specifies that reads and writes to the mapping +may be weakly ordered, that is that reads and writes may pass each other. + +Since it is optional for platforms to implement DMA_ATTR_WEAK_ORDERING, +those that do not will simply ignore the attribute and exhibit default +behavior. |