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| author | Mark Langsdorf <mark.langsdorf@amd.com> | 2009-04-09 15:31:53 +0200 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2009-04-10 14:22:40 +0200 |
| commit | 2fad2d9bb8310889f3261035b594b4e068b6eb8b (patch) | |
| tree | 3434e3c0a280b10c73b81e7af3c37e23209f0dec /Documentation/ABI | |
| parent | ba518bea2db21c72d44a6cbfd825b026ef9cdcb6 (diff) | |
| download | op-kernel-dev-2fad2d9bb8310889f3261035b594b4e068b6eb8b.zip op-kernel-dev-2fad2d9bb8310889f3261035b594b4e068b6eb8b.tar.gz | |
x86/docs: add description for cache_disable sysfs interface
Signed-off-by: Mark Langsdorf <mark.langsdorf@amd.com>
Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
LKML-Reference: <20090409133153.GL31527@alberich.amd.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'Documentation/ABI')
| -rw-r--r-- | Documentation/ABI/testing/sysfs-devices-cache_disable | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/Documentation/ABI/testing/sysfs-devices-cache_disable b/Documentation/ABI/testing/sysfs-devices-cache_disable new file mode 100644 index 0000000..175bb4f --- /dev/null +++ b/Documentation/ABI/testing/sysfs-devices-cache_disable @@ -0,0 +1,18 @@ +What: /sys/devices/system/cpu/cpu*/cache/index*/cache_disable_X +Date: August 2008 +KernelVersion: 2.6.27 +Contact: mark.langsdorf@amd.com +Description: These files exist in every cpu's cache index directories. + There are currently 2 cache_disable_# files in each + directory. Reading from these files on a supported + processor will return that cache disable index value + for that processor and node. Writing to one of these + files will cause the specificed cache index to be disabled. + + Currently, only AMD Family 10h Processors support cache index + disable, and only for their L3 caches. See the BIOS and + Kernel Developer's Guide at + http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/31116-Public-GH-BKDG_3.20_2-4-09.pdf + for formatting information and other details on the + cache index disable. +Users: joachim.deguara@amd.com |
