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author | Olof Johansson <olof@lixom.net> | 2018-05-14 13:28:11 -0700 |
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committer | Olof Johansson <olof@lixom.net> | 2018-05-14 13:28:11 -0700 |
commit | 08a5f1ac35b0a42e4edece0cda2a79d2fe92fa03 (patch) | |
tree | bedfcba0a39fc10f614a1ac25ecbce1881c0072c /CREDITS | |
parent | e5d9875ecd2e75b30d906c480ccc1896948e2d03 (diff) | |
parent | 56e4446df9c1214e886fdc7603a5c1cb99cb1843 (diff) | |
download | op-kernel-dev-08a5f1ac35b0a42e4edece0cda2a79d2fe92fa03.zip op-kernel-dev-08a5f1ac35b0a42e4edece0cda2a79d2fe92fa03.tar.gz |
Merge tag 'arm-soc/for-4.18/soc' of https://github.com/Broadcom/stblinux into next/soc
This pull request contains Broadcom ARM-based machine/platform files
changes for 4.18, please pull the following:
- Doug updates arch/arm/include/asm/cpuinfo.h such that this header file
can be used by both C and assembly code. This particular change will
also be included in a Sunxi pull request to support A83T SMP support.
- Doug also updates our DEBUG_LL routine to support newer chips such as
7278 which have a version 7 memory map which moves the registers from
physical address 0xf000_0000 down to 0x0800_0000. This requires us to
look up the processor MIDR and determine the base address from the
PERIPHBASE register.
- Florian updates the Brahma-B15 read-ahead cache implementation such
that it works on the Brahma-B53 CPUs, which also have an identical
read-ahead cache implementation, with a different set of offsets. He
also provides the Brahma-B15 MIDR definition such that it can be used by
other pieces of code in the future.
* tag 'arm-soc/for-4.18/soc' of https://github.com/Broadcom/stblinux:
ARM: brcmstb: Add support for the V7 memory map
ARM: add Broadcom Brahma-B15 main ID definition
ARM: add Broadcom Brahma-B53 main ID definition
ARM: Allow this header to be included by assembly files
ARM: B15: Update to support Brahma-B53
Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'CREDITS')
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