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authorBruce Allan <bruce.w.allan@intel.com>2010-05-05 22:00:06 +0000
committerDavid S. Miller <davem@davemloft.net>2010-05-06 01:31:28 -0700
commit6dfaa76994e5d49a82afb415bbe1362e901b2b95 (patch)
treeab1629de17f4d8763343b6d53ee58a674bb7d2e4 /COPYING
parentffb273623bc506d854902a415ef241b79232f93a (diff)
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op-kernel-dev-6dfaa76994e5d49a82afb415bbe1362e901b2b95.tar.gz
e1000e: reset MAC-PHY interconnect on 82577/82578 during Sx->S0
During Sx->S0 transitions, the interconnect between the MAC and PHY on 82577/82578 can remain in SMBus mode instead of transitioning to the PCIe-like mode required during normal operation. Toggling the LANPHYPC Value bit essentially resets the interconnect forcing it to the correct mode. Signed-off-by: Bruce Allan <bruce.w.allan@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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