diff options
| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2016-06-10 09:36:44 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2016-06-21 09:21:05 +0200 |
| commit | f7bb887fb898307dd575179303b710d933f242ea (patch) | |
| tree | b190bdf332f5ce150e1e9ced5b082aaf149ca670 | |
| parent | a20956804220951196671ed5455d085927d6a754 (diff) | |
| download | op-kernel-dev-f7bb887fb898307dd575179303b710d933f242ea.zip op-kernel-dev-f7bb887fb898307dd575179303b710d933f242ea.tar.gz | |
clk: renesas: r8a7795: Correct lvds clock parent
According to the latest information, the parent clock of the LVDS module
clock is the S0D4 clock, not the S2D1 clock.
Note that this change has no influence on actual operation, as the
rcar-du LVDS encoder driver doesn't use the parent clock's rate.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
| -rw-r--r-- | drivers/clk/renesas/r8a7795-cpg-mssr.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c index 8f76af6f..ad01b0b 100644 --- a/drivers/clk/renesas/r8a7795-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c @@ -180,7 +180,7 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = { DEF_MOD("du2", 722, R8A7795_CLK_S2D1), DEF_MOD("du1", 723, R8A7795_CLK_S2D1), DEF_MOD("du0", 724, R8A7795_CLK_S2D1), - DEF_MOD("lvds", 727, R8A7795_CLK_S2D1), + DEF_MOD("lvds", 727, R8A7795_CLK_S0D4), DEF_MOD("hdmi1", 728, R8A7795_CLK_HDMI), DEF_MOD("hdmi0", 729, R8A7795_CLK_HDMI), DEF_MOD("vin7", 804, R8A7795_CLK_S2D1), |
