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authorRoy Spliet <r.spliet@student.tudelft.nl>2012-02-07 00:29:06 +0100
committerBen Skeggs <bskeggs@redhat.com>2012-03-13 17:14:59 +1000
commite6084257d07fffc394ac6e4cf4496c946fd904ed (patch)
treee360a34ed372efcb538d690889c7d00d396df83e
parent1ae73f2f16f1a905ada71e2a190d5760b4f17ed8 (diff)
downloadop-kernel-dev-e6084257d07fffc394ac6e4cf4496c946fd904ed.zip
op-kernel-dev-e6084257d07fffc394ac6e4cf4496c946fd904ed.tar.gz
drm/nouveau/pm: several fixes for nvc0 memory timings
This patch fixes two small issues in timing generation as spotted on several NVCx cards. In addition, the header of the file is updated to also contain (some of) the current developers of this code. Signed-off-by: Roy Spliet <r.spliet@student.tudelft.nl> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_mem.c9
1 files changed, 6 insertions, 3 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_mem.c b/drivers/gpu/drm/nouveau/nouveau_mem.c
index 8ff0027..b08065f 100644
--- a/drivers/gpu/drm/nouveau/nouveau_mem.c
+++ b/drivers/gpu/drm/nouveau/nouveau_mem.c
@@ -26,7 +26,8 @@
* DEALINGS IN THE SOFTWARE.
*
* Authors:
- * Keith Whitwell <keith@tungstengraphics.com>
+ * Ben Skeggs <bskeggs@redhat.com>
+ * Roy Spliet <r.spliet@student.tudelft.nl>
*/
@@ -613,13 +614,13 @@ nvc0_mem_timing_calc(struct drm_device *dev, u32 freq,
t->reg[1] = (boot->reg[1] & 0xff000000) |
(e->tRCDWR & 0x0f) << 20 |
(e->tRCDRD & 0x0f) << 14 |
- (e->tCWL << 7) |
+ (t->tCWL << 7) |
(e->tCL & 0x0f);
t->reg[2] = (boot->reg[2] & 0xff0000ff) |
e->tWR << 16 | e->tWTR << 8;
- t->reg[3] = (e->tUNK_20 & 0xf) << 9 |
+ t->reg[3] = (e->tUNK_20 & 0x1f) << 9 |
(e->tUNK_21 & 0xf) << 5 |
(e->tUNK_13 & 0x1f);
@@ -930,6 +931,8 @@ nouveau_mem_timing_read(struct drm_device *dev, struct nouveau_pm_memtiming *t)
t->tCWL = 0;
if (dev_priv->card_type < NV_C0) {
t->tCWL = ((nv_rd32(dev, 0x100228) & 0x0f000000) >> 24) + 1;
+ } else if (dev_priv->card_type <= NV_D0) {
+ t->tCWL = ((nv_rd32(dev, 0x10f294) & 0x00000f80) >> 7);
}
t->mr[0] = nv_rd32(dev, mr_base);
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