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| author | Sujith Manoharan <c_manoha@qca.qualcomm.com> | 2015-03-09 14:20:06 +0530 |
|---|---|---|
| committer | Kalle Valo <kvalo@codeaurora.org> | 2015-03-13 15:19:28 +0200 |
| commit | e519f78f1191007604c056dfcb372d4fe3a4b05b (patch) | |
| tree | 4afce2fa31bf040487ab4c09f8286307b925f49a | |
| parent | 02beaf1a5b8f05ead295d781522b1684dc5e7263 (diff) | |
| download | op-kernel-dev-e519f78f1191007604c056dfcb372d4fe3a4b05b.zip op-kernel-dev-e519f78f1191007604c056dfcb372d4fe3a4b05b.tar.gz | |
ath9k: Add PCIE powersave macros
These will be used to handle chip-specific
power save configuration.
Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
| -rw-r--r-- | drivers/net/wireless/ath/ath9k/hw.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h index 29a25d9..2bb3b33 100644 --- a/drivers/net/wireless/ath/ath9k/hw.h +++ b/drivers/net/wireless/ath/ath9k/hw.h @@ -309,6 +309,12 @@ enum ath9k_hw_hang_checks { HW_MAC_HANG = BIT(5), }; +#define AR_PCIE_PLL_PWRSAVE_CONTROL BIT(0) +#define AR_PCIE_PLL_PWRSAVE_ON_D3 BIT(1) +#define AR_PCIE_PLL_PWRSAVE_ON_D0 BIT(2) +#define AR_PCIE_CDR_PWRSAVE_ON_D3 BIT(3) +#define AR_PCIE_CDR_PWRSAVE_ON_D0 BIT(4) + struct ath9k_ops_config { int dma_beacon_response_time; int sw_beacon_response_time; |
